# Lecture 6 - State - flip-flops

## Practical Details

1. Assignment 1.

# State

## SR Flip-flop

Two inputs

1. S: Set
2. R: Reset

Output Q

#### Truth table

```S R P Q
F F T F
F T
T F F T
F T T F
T T F F
```

On S: F -> T sets Q to T, P to F

On T: F -> T resets Q to F, P to T

In other words, by briefly, whatever that means in practice, asserting S or R you put the SR flip-flop into a state in which it remains until next set or reset. That is, it remembers what happened most recently to it.

#### SR flip-flop instability

Consider the transition from (SR)=(TT) to (SR)=(FF)

• The outputs oscillate
• The frequency of the oscillation depends on the gate delay
• If the oscillation happens to be damped, then the flip-flop falls into a random state
• So we have to forbid such an input, because its result is undesirable.

## Clocked Logic

Why is a clock important?

1. gate delays

What kind of chip provides a clock?

• piezo-electric crystal

Why is the clock difficult to implement?

• clock skew

## D Latch

We will now modify the flip-flop so that it samples its input when it gets a clock input

Two inputs:

1. D: Data
2. C: Clock

Outputs: Q Qbar

Clock high: output follows input

Clock low: output stays constant

The latch samples the input on the high to low clock transition, then holds it

Where might you use a latch?

Do the exercises on pp. 13-14 of the notes.

## D Flip-flop

Two D-latches in a master-slave configuration.

## Registers

Arrays of D flip-flops all clocked by the same clock.

#### Register file

Just a collection of registers