CS251 - Computer Organization and Design - Spring 2008
Lecture 8 - State - flip-flops
Practical Details
- Assignment 1.
State
D Flip-flop
Two D-latches in a master-slave configuration.
- The master-slave samples on the clock transition.
- `Is there such a thing as a flip-flop that is not a master-slave
flip-flop?'
Registers
Arrays of D flip-flops all clocked by the same clock.
Register file
Just a collection of registers
Read-write logic
Three-state Outputs
A bus, by definition, can be driven by more than one source. How can this
be done?
Example: SRAM
Two bits of address, two bits of data.
SRAM is used for cache memory because it is
- expensive
- fast
- refresh-free
DRAM
Error in the notes. Page 18, bottom, should read.
- Transistor is a switch
- When the word line is asserted the switch is closed.
- Otherwise it's open.
- Closed switch transfers charge.
- Bit line transfers charge to capacitor on write
- Capacitor transfers charge to bit line on read
- Bit line is half way between high and low.
- Open switch
- Holds charge on capacitor
- Keeps impedance of connection to bit line high
DRAM Refresh
- Charge slowly drains away, weakening the signal.
- Read, which weakens state further
- Rewrite, which makes it new again.
Typical to refresh once every few milliseconds
- Refresh occurs part of a memory chip at a time, and that part is not
available for reading or writing while the refresh takes place.
Error in notes. Page 19, line starting `If capacitors ...' should read
- Capacitors hold charge well-enough that they need to be refreshed every
few milliseconds, say 4 milliseconds to be concrete.
- Refresh takes less than 20 to 50 microseconds
- Therefore the memory is unavailable for about 2% of the time.
SSRAM and SDRAM
The first `S' stands for synchronized.
Controllers Based on Finite State Machines.
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