CS251 - Computer Organization and Design - Spring 2008

Lecture 8 - Finite state machines


Practical Details

  1. Assignment 1.
  2. Assignment 2.
  3. Next Friday.

State

SRAM

Based on the D latch with three state output

Write:

Read:

Two bits of address, two bits of data.

SRAM is used for special (low power, cache, etc) memory because it is

Controllers Based on Finite State Machines.

Ingredients

  1. Clock
  2. Register to hold state, sampled by clock
  3. Inputs
  4. Outputs
  5. Logic to compute next state and outputs from this state and inputs.

Controllers use the simplest way of addressing memory

More scalable, and more complex ways of addressing use binary-coded addresses with a common data bus using

DRAM

Error in the notes. Page 18, bottom, should read.

DRAM Refresh

  1. Charge slowly drains away, weakening the signal.
  2. Read, which weakens state further
  3. Rewrite, which makes it new again.

Typical to refresh once every few milliseconds

Error in notes. Page 19, line starting `If capacitors ...' should read

SSRAM and SDRAM

The first `S' stands for synchronized.


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