# Lecture 15 - Single-Cycle Processor

## Practical Details

1. Read 5.1 to 5.4, C.2

# Floating Point Numbers

## Algorithms for Addition and Multiplication

1. Equalize exponents
1. Shift right significand of number with smaller exponent
2. Add 1 to its exponent
3. Until exponents are equal
1. Put one bit bit 23
2. Use sign bit top create TCIs
3. Sign extend
4. Add as TCIs: extra precision not needed
3. Normalize result
1. Shift significand left or right
2. Add 1 to or subtract 1 from exponent
3. Until significand is normalized

Note that subtraction is different

#### Multiplication (Division)

2. Multiply significands
3. Normalize result

#### Pathologies

Exponent can overflow or underflow.

Significand can underflow

#### NaN (Not a Number)

Possible values

1. Too large to represent
2. Too small to represent
3. Infinity
4. Underflow

# Single-Cycle Processor

Datapath & control for a mini-MIPS (MIPS = Multiprocessor without Interlocked Pipeline Stages). Operations

2. add, subtract, AND, OR, set on less than
3. jump and conditional branch

which is enough to write just about any program.

Exercise: What is missing? (Answer. Shift)

#### MIPS Architecture

32 32-bit registers, numbered 0 to 31

• R0 = x00000000 always

Memory of 32-bit words

• data paths are 32-bit

All instructions are 32-bit

#### Instructions

• register, \$s1
• base + displacement, 100(\$s1)
• immediate, 100
2. load: `lw \$s1, 100(\$s2)` - load into register 1 whatever is 100 bytes from the value in register 2
3. store: `sw \$s1, 100(\$s2)` - store the contents of register 1 into the memory at 100 bytes from the value in register 2

1. add: `add \$s1, \$s2, \$s3` - add the values in regusters 2 and 3 and put the result in register 1

Conditional branch

1. branch on equal: `beq \$s0, \$s1, 10` - is the value in register 0 equals the value in register 1 set PC <= PC + 4 + 40

Unconditional branch

1. jump: `j 1000` - PC <= 4000

#### MIPS Functional Units

1. Program counter (PC) used to fetch instruction from instruction memory
2. Instruction used to fetch register operands from register file
3. Instruction plus registers used to fetch memory operands from data memory
4. ALU computes result
5. Result put into register file or data memory

# Instruction Execution Components

The more you can keep them separate the more you can

• parallelize
• pipeline

## Instruction Fetch

#### Sequence

1. Signal to fetch
3. Increment PC by 4 (combinational logic)

Often there is a FIFO

#### Datapaths

1. PC to memory
4. Instruction to next stage

#### Decode Instruction and route the parts accordingly

Instruction Types

1. Register instructions
2. Memory instructions
3. Branch instructions

## Register (R-type) Instructions

1. Argument parts of instruction select read and write registers
2. ALU part of instruction selects operation of ALU

#### Sequence

1. Read arguments of instruction put register values on path to ALU input
2. ALU part of instruction selects the combination logic function to be applied
3. Result appears on ALU output
4. ALU output written to register selected by argument

#### Datapaths

1. Instruction to register file
2. Instruction to ALU
3. Register file to ALU input
4. ALU output to register file