CS251 - Computer Organization and Design - Spring 2008

Lecture 22 - Intreoduction to Multiple Cycle Designs


Practical Details

  1. Exam results
  2. Assignment this week

Single Cycle Weaknesses

Control Logic

Seems pretty ad hoc.

Extensibility

See above

Timing

Different cycles take different amounts of time

Pipelining

Phases of instruction execution

  1. Instruction fetch & decode
  2. Operand values
  3. Result calculation
  4. Result writeback

We would like to get these separated from one another,

And yet,

The most popular processor architecture in the world is a single cycle one

Which brings up a MIPS oddity

No condition codes

MIPS uses the set instruction followed by conditional branch


Multicycle Execution

Separating the phases

Instruction Fetch

Store instruction in register

Increment PC using ALU

Evaluating Operands

Put operands into registers, which are input to



Control Logic

Highest six bits of instruction is opcode

Control logic needs to accept opcode (26:31) and function (0:5)

Split into two stages

  1. From opcode only generate all control signals except ALUctl, plus ALUop
  2. From ALUop plus function generate ALUctl

Signals to generate

Signal 0 1
RegDst rt rd
RegWrite n/a write register
ALUSrc register instruction
Branch no branch branch
MemRead n/a read memory
MemWrite n/a write memory
MemToReg write register from ALU write register from memory
ALUOp0 not branch branch
ALUOp1 not R-type R-type

Opcodes

Opcode Instruction Assert
100011 lw ALUSrc, MemToReg, RegWrite, MemRead
101011 sw ALUSrc, MemWrite
000100 beq Branch, ALUOp0
000000 R-format RegDst, RegWrite, ALUOp1

ALUCtl

Operation ALUOp Funct action ALUCtl
beq 01 XXXXXX subtract 110
add 10 100000 add 010
sub 10 100010 subtract 110
and 10 100100 AND 000
or 10 100101 OR 001
slt 10 101010 set on less than 111

Timing

Suppose

Then for R-type instructions

But for loads

And for conditional branches

Climax

The CPU plus memory is just a finite state machine, albeit a complex one.


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