CS251 - Computer Organization and Design - Spring 2008

Lecture 23 - Multiple Cycle Designs


Practical Details

  1. Optional assignment
  2. Read 5.5, C.3, C.4

Multicycle Execution

The Basic Idea

Datapaths and Registers

  1. PC(reg) to memory to Instruction(reg)
  2. Instruction(reg) to
  3. Operands
  4. ALUout to

Use of ALU

  1. all instructions: PC++
  2. conditional branch: PC + immediate

Add MUXes

  1. Memory address: PC or ALUout
  2. Register file write register: inst16-20 or inst11-15
  3. ALUinpA: PC or operandA
  4. ALUinpB:
  5. PC:

Control Signals

One-bit

Signal name 0 1 Comment 1 2 3R 3M 3B 4R 4M 5
RegDst write to rt write to rd MUX2 X X X X X 1 X 0
RegWrite write to register X X X X X 1 X 1
ALUSrcA PC register A MUX4 0 0 1 1 1
MemRead read from memory 1 1
MemWrite write to memory X
MemToReg data from ALU data from memory MUX3 0 1
IorD address from PC address from ALU MUX1 0 1
IRWrite latch instruction register 1
PCWrite write PC 1
CondPCWrite write PC if ALUout = 0 1

Two-bit

Signal Value Effect 1 2 3E 3M 3B 4 5
ALUOp 00 add S S S S
01 subtract S
10 determine by funct
ALUSrcB 00 input from register B S
01 input is 4 S
10 input is immediate field S S
11 input is shifted immediate field S
PCSource 00 PC from ALUout S
01 PC from ALUOut S
10 PC gets jump target from immediate


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