CS251 - Computer Organization and Design - Spring 2008

Lecture 26 - Multi-cycle Control


Practical Details

  1. Assignment 6

Multi-cycle Control

The Basic Idea

  1. You have already put in the
  2. Work out the control signal values for each state.
  3. Make a finite-state machine

This is done in detail in both the notes and in the text-book. Sometimes the details are a little sketchy, but you should be able to fill in the blanks by this point. This is what you have to do in order to master the material.

Assignment 6, which asks you to give datapaths and control cycles for a much simpler will give you some indication how well you are doing.

Control Signals

One-bit

Signal name 0 1 Comment 1 2 3R 3M 3B 4R 4M 5
RegDst write to rt write to rd MUX2 X X X X X 1 X 0
RegWrite write to register X X X X X 1 X 1
ALUSrcA PC register A MUX4 0 0 1 1 1
MemRead read from memory 1 1
MemWrite write to memory X
MemToReg data from ALU data from memory MUX3 0 1
IorD address from PC address from ALU MUX1 0 1
IRWrite latch instruction register 1
PCWrite write PC 1
CondPCWrite write PC if ALUout = 0 1

Two-bit

Signal Value Effect 1 2 3E 3M 3B 4 5
ALUOp 00 add S S S S
01 subtract S
10 determine by funct
ALUSrcB 00 input from register B S
01 input is 4 S
10 input is immediate field S S
11 input is shifted immediate field S
PCSource 00 PC from ALUout S
01 PC from ALUOut S
10 PC gets jump target from immediate

Implementation

Either

  1. Combinational logic: fast, small, inflexible
  2. Programmable logic array (PLA): fast, big, more flexible
  3. Read-only memory (could be flash): slower, very big, yet more flexible
  4. Micro-code: faster or slower, small, the most flexible

Micro-code

Anything we can make with a finite state machine we can make with a program.

This has re-entered CS hardware with a new name

Exceptions

What do we do when

  1. an external event needs to be accepted by the processor
  2. something screwy happens, like an address fault

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