CS251 - Computer Organization and Design - Spring 2008

Lecture 28 - Hazards


Practical Details

  1. Assignment 7
  2. Read Chapter 6 in the textbook

Pipelining

We made each instruction into a sequence of phases

  1. instruction fetch, uses
  2. instruction decode and operand generation, uses
  3. execute: split across instruction type

    uses

  4. memory access: M-type only, uses
  5. writeback to register: R-type, M-type, uses

For good pipelining

Make all phases of instruction execution the same length

  1. One instruction length
  2. Few instruction formats
  3. Restricted memory access

Comparison

Single-cycle Multi-cycle Pipelined
Instruction types 3 3 3
Instruction lengths 1 slow cycle 3,4,5 fast cycles 5 fast cycles
Instruction issue 1 per cycle 1 per weighted average 1 per cycle
ALUs 2 slow, 1 fast 1 fast 3 fast
Memories 2 1 2

Read chapter 6.2, looking carefully at each diagram.

Control signals

The idea here is simple in principle, but complicated in practice.

If there are five instructions in the pipeline we need five sets of control signals, one set for each instruction.

  1. The instruction in phase 1 needs to get phase 1 control signals
  2. Other instructions are generating phase 2 to 5 control signals
  3. The phase 2-5 control signals need to be kept away from the hardware being used for phase 1


Hazards

Any condition that blocks the flow of instruction through the pipeline

Structural Hazards

Hardware prevents two phases from overlapping

This means that we are working with the hardware of the single-cycle processor

Draw synchronization blocks where phases end

Drawing pipelines
1. When we draw instruction execution in a pipeline the emphasis is on the resources being used. Thus, we draw the resource being used in each pipeline step.

2. You should notice something fishy: the register file is used in the second and fifth phase of processing:

  • in the second to get operands
  • in the fifth to write back data.

Surely these phases cannot overlap.

3. The solution is to separate phases two and five into a early and a late phase.

  • Registers are accessed in the late part of phase 2
  • Registers are accessed in the early part of phase 5.

4. In drawings the early and late phase are differentiated by separating by drawing register use in only half the phase, as is done for instruction memory, data memory and register file throughout Chapter 6 of the textbook.

5. Note that the schematic registers (long horizontal rectangles) are highlighted on the left side when they are accepting data from the previous phase, and on the right side when they are providing stabilized data to the next phase.

Control Hazards

Don't know PC in time for next instruction fetch

Possible solutions

  1. Stall
  2. Delayed branch
  3. Static branch prediction
  4. Dynamic branch prediction

Data Hazards

Result of one instruction needed in the next one.


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