# Lecture 29 - Data Hazards

## Practical Details

1. Assignment 7
2. Control signals in pipelined execution

# Hazards

Any condition that blocks the flow of instructions through the pipeline

## Data Hazards

Result of one instruction needed in the next one.

#### Example

```sub \$2, \$1, \$3
and \$12, \$2, \$5
or \$13, \$6, \$2
add \$14, \$2, \$2
sw \$15, 100(\$2)
```

#### Solution 1: Compiler

Ask the compiler to reorder instructions

• nice, but can't always be done

#### Solution 2: Subphases

Write registers early in the phase

• read them late in the phase
• gets rid of one of the hazards

#### Solution 3: Forwarding

Classify remaining hazard types using the notation

• <Phase boundary>.<register getting result> => <Phase boundary>.<register giving operand>
• only rd for results
• only rs, rt for operands
• only decode&operand/execute for operands
• only execute/memory and memory/writeback for results

Labels

• 1a EX/MEM.Rd => ID/EX.Rs
• 1b EX/MEM.Rd => ID/EX.Rt
• 2a MEM/WB.Rd => ID/EX.Rs
• 2b MEM/WB.Rd => ID/EX.Rt

Data actually produced in phase 3

• and only needed in phase 3 of the following instruction
• forward them along by adding extra data paths that inter-instruction dependencies

Requires

• dependency detection by the hardware
• new data paths for every possible dependency
• new multiplexors to switch the data paths
• instruction decode that considers more than one instruction/phase at a time.

Solves type 1 hazards

#### Solution 4: Stalls

Consider

```lw  \$2, 100(\$1)
and \$12, \$2, \$5
or  \$13, \$6, \$2
add \$14, \$2, \$2
sw  \$15, 100(\$2)
```

The result of the first instruction is available only at the end of the memory phase

• not available, even by forwarding, to the second instruction
• no option but to put in a nop
• This is called a stall.

Interesting sidelight.

• It isn't possible to know that a stall is needed until the instruction has been read
• So putting a nop means starting the
• second instruction,
• aborting it, then
• immediately starting it again

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