CS251 - Computer Organization and Design - Spring 2008

Lecture 30 - Memory


Practical Details

  1. Assignment 7
  2. Finished pipelined execution

Performance

The numbers below vary with architecture

Clock Cycles/instruction Instructions/clock Hazards Hardware

required

Compiler

assistance*

Memory

assistance**

Single-cycle 5 5 1 none 3 ALU,

2 memory

No Yes
Multi-cycle

1

3-5

3x+4y+5z

x+y+z = 1

none 1 ALU,

1 memory

A little No
Pipelined

1

1

1+w

w: fraction of instructions that stall

Structure

Control

Data

3 ALU

2 memory

A lot Yes

* but must be able to cope with code produced by any compiler.

** hardware support for separate instruction and data access.


Memory Hardware

Registers

Cache

May have nore than one level

Main Memory

Disk

Internet

Also Available

Flash Ram, NVRam

RamDisk

Hardware Performance

Access time

(nsec)

Cost

per Gbyte

Notes
Registers 0.1 Can't separate cost from remainder of processor
Cache (SRAM) 0.1 - 1.0 $4000.00 Big on-chip, off-chip differences
Main memory (DRAM) 50 - 70 $100.00 SDRAM is faster in bursts
Ramdisk (based on NVRam) read: 10.0

write: 10,000.0

$5.00 Inadequate capacity for demand.

Many competing technologies.

Limited number of memory cycles.

Disk seek: 5,000,000

continuous: ~100

$0.50
Internet infinity free

Memory Concepts

Locality

Block

Cache


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