CS452 - Real-Time Programming - Fall 2009

Lecture 14 - AwaitEvent

Reminders


Interrupt Servicing

How to do it

  1. Find source of the interrupt
  2. Save state of interrupted task
  3. Restore kernel state
  4. EITHER, process interrupt in kernel
    1. acquire volatile data from device
    2. turn off interrupt source
      • in device
      • in PIC
    3. set up return value for AwaitEvent
    4. schedule
    5. exit from kernel
      • movs, or equivalent, moves SPSR to CPSR
      • goes to user mode
      • turns on interrupts

    OR, process interrupt in notifier

    1. exit, without scheduling, to notifier in svc mode
    2. acquire volatile data from device
    3. turn off interrupt source
      • in device
      • in PIC
    4. turn on interrupts & return to user mode in one instruction

Your code should operate correctly if there is another interrupt waiting which is taken immediately after interrupts are enabled.


The ARM Interrupt Controller

How OSs Handle Interrupts

  1. ISRs that do all the work
  2. ISRs that work asynchronously
  3. ISRs that trigger other processes

Interrupt Handling Methods

Monolithic ISRs Signals Task chains Comments
Non-nested Yes Yes No: User tasks interruptable Better not be very much to do.

Test interrupt sources in order of priority.

Nested Not usually No. Trying to do minimal work Yes: prioritized within task structure Not very useful without priorities elsewhere

Interrupts block-structured

Prioritized Nested When there is too much to do. No. Trying to do minimal work Interruptable kernel, OR free with prioritized tasks Hard to get right

Do only higher priority nested

Prioritized: software No No Yes Minimal interruption for lower priority
Prioritized: hardware Yes, if processing is long Yes, for simultaneous interrupts Yes, for simultaneous interrupts No interruption for lower priority
Vectored, with priority Yes, for speed Yes, for speed Not usually worth it This cuts out polling of the interrupt controller and the devices.

Registers: General

ARM Specific

Two controllers, daisy-chained

Registers at

47 registers per controller

Priority

  1. FIQ-configured interrupts (not vectored)
  2. IRQ-configured vecored interrupts
  3. IRQ-configured non-vectored interrupts

Useful Tricks

Software Interrupt

Making programming easier

  1. SWI,
  2. VICxSoftInt & VICxSoftIntClear

HALT versus Idle Task

What do you do when there are no tasks to run?

HALT


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