CS452 - Real-Time Programming - Fall 2010

Lecture 5 - Context Switches on the Arm

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Doing It on the ARM

ARM 920T

What is this?

Two modes of labelling

  1. By architecture
    Architecture Instruction

    Set

    Thumb

    Instructions?

    Multiply

    Instruction

    DSP

    Instructions

    Comments
    ARMv1 1 no no no Obsolete
    ARMv2 2 no no no Obsolete
    ARMv3 3 no no no
    ARMv3M 3 no yes no
    ARMv4 4 no yes no
    ARMv4T 4 yes yes no This is the one in the box.
    ARMv5 5 no yes no Has CLZ
    ARMv5T 5 yes yes no
    ARMv5TE 5 yes yes yes

    Thumb instructions are 16 bit, and accelerated.

  2. By processor core
    Processor

    Core

    ARM

    ISA

    Thumb

    ISA

    Comments
    ARM7TDMI v4T v1 Most of the ARM7xx processors
    ARM9TDMI v4T v1 ARM[920|922|940]T: 920T is the one in the box.

    `T' means includes thumb instructions

    `DMI' means direct memory interface

    StrongARM v4 n/a Intel SA-110. Found in Compaq versions of IPAQ.
    ARM9E v5TE v2
    ARM10E v5TE v2
    XScale v5TE v2 Manufactured by Intel. HP versions of IPAQ.

Features

  1. 16 32-bit registers

    partially separate register sets different modes

    link register (lr), program counter (pc) are special, but not very special

  2. Exceptions
    Exception

    Type

    Processor

    Mode

    Instruction

    Address

    Reset supervisor 0x00
    Undefined instruction undefined 0x04
    Software interrupt supervisor 0x08
    Prefetch abort abort 0x0c
    Data abort abort 0x10
    Ordinary interrupt IRQ 0x18
    Fast interrupt FIQ 0x1c

    1. You are concerned right now with Reset and Software Interrupt.
    2. The first instruction executed by the CPU after reset is the one at location 0x00000000. Usually it is
          ldr  pc, [pc, #0x18] ; 0xe590f018 is the binary encoding

      which you will normally find in addresses 0x00 to 0x1c.

    3. It puts the entry point of RedBoot into addresses 0x20 to 0x3c.
    4. Note endianness of RedBoot output when examining these locations.
  3. Three data types
  4. Program status register, which you will find in two places CPSR and SPSR
    Bit Mnemonic Meaning
    31 N Negative
    30 Z Zero
    29 C Carry
    28 V Overflow
    8-27 DNM Does not matter in v4
    7 I Interrupts disabled
    6 F Fast interrupts disabled
    5 T Thumb execution
    4 M4 Five processor mode bits
    3 M3
    2 M2
    1 M1
    0 M0
  5. Processor modes
    M[4:0] Mode Registers accessible
    10000 User
    10001 FIQ (Fast interrupt processing)
    10010 IRQ (Interrupt processing)
    10011 Supervisor
    10111 Abort
    11011 Undefined
    11111 System

General Comments

  1. each instruction is exactly one word
  2. load and store RISC architecture
  3. rich set of addressing modes
  4. allows you to keep any partial computation it makes

Context Switch

Step-by-step

Function Call

; In calling code
   bl  <entry point>  ; this treats the pc and lr specially

; In called code
entry point:
   mov     ip, sp
   stmdb   sp!, {fp, ip, lr} ; and usually others, 
                             ; determined by the registers the function uses
                             ; optimizer changes this instruction
   ...
   ldmia   sp, {fp, sp, pc} ; and whatever others
                            ; exact inverse of stmdb

Note the role of the index pointer (ip), link register (lr) and stack pointer (bl).

Software Interrupt

; In calling code
   swi  n                 ; n identifies which system call you are calling

; In kernel
kernel entry:
; Change to system mode
; Save user state on user stack
; Return to supervisor mode
   ldr    r4, [lr, #-4]    ; gets the request type
                           ; at this point you can get the arguments
                           ; Where are they?
; Retrieve kernel state from kernel stack
; Do kernel work

Questions:

  1. What is above kernel entry?
  2. If you put swi in a wrapper or stub what happens before and after it?
  3. If the request had arguments, how would you get them into the kernel?

    Hint. How does gcc pass arguments into a function?

  4. It might be important that there are two link registers. Which two link registers? Why?
  5. In practice it isn't important. Why not?

Suggestions:

  1. Try this first on paper drawing the stack, registers, etc after each instruction
  2. Try coding in baby steps, which is usually a good idea in assembly language.

Try reading this.


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