CS452 - Real-Time Programming - Fall 2010

Lecture 16 - UART Interrupts

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The Little Blunder

You may have already read the following.

`It is assumed that various configuration registers for the UART are not written more than once in quick succession, in order to insure proper synchronization of configuration information across the implementation. Such registers include UART1Ctrl and UART1LinCtrlHigh. ... In between the two writes, at least two UARTCLK periods must occur. Under worst case conditions, at least 55 HCLK periods must separate the two writes. The simplest way to due [sic] this is separate the two writes by 55 NOPs.'

Why does this occur?

Why doesn't anybody care about blunders?


Five interrupts in the device

  1. Transmit
  2. Receive
  3. Modem status
  4. Receive timeout
  5. Combined

Three inputs to the PIC

  1. Transmit
  2. Receive
  3. Combined

Easy way to use interrupts

Enable only combined; read UART registers to decide what to do.

Think of the receive and transmit parts of the UART as separate state machines

Handy Features


The simplest way to handle the interrupts is to turn on only the combined interrupt and then look at the registers of the device.

To identify the current interrupt

Read UARTxIntIDIntClr at 0x800[bc]001c

When service is required, without FIFO.


  1. Initialization
  2. When bytes arrive to transmit
  3. On transmit interrupt
  4. On modem status interrupt


  1. Receive interrupt

Using the FIFO

Left as an exercise.

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