CS452 - Real-Time Programming - Fall 2011

Lecture 12 - Hardware Interrupts II

Public Service Annoucements

  1. Due date of kernel 3 (Monday, 17 October)

Hardware Interrupts

Up to this point the kernel is not able to accept input from the outside world, or to affect the outside world. Thus, the possibility of an event occurring that must be followed by a timely response is not an issue. Hardware interrupts change that rosy world.

In a distant era of CPU design (somewhere around the MC68000) the interrupt changed its status from afterthought to crucial in the designer's mind. Its name also changed, from `interrupt' to `exception'.

What is a Hardware Interrupt?

The first issue is level versus edge dependent.

In the CPU

  1. Test interrupt input, IRQ, before fetching the next instruction
  2. If asserted, change mode to IRQ
  3. Disable interrupt in CPSR
  4. Execute instruction at 0x18

In the Interrupt Control Unit (ICU)

In the Peripheral Hardware

When two interrupts are present

May have been two present when interrupt processing started

May have occurred since interrupt processing started

What happens next? Whatever the case,

  1. Kernel executes with interrupts disabled
  2. Context switch into user task turns on interrupts
  3. Before fetching the first user task instruction test interrupt signal
  4. It is asserted, interrupt processing restarts immediately

For this behaviour to do the job the time spent inside the kernel must be small compared to latencies acceptable to the objectives of the application.

Context Switches for Interrupts

Difference from Software Interrupts

It is impossible to predict where they occur

Assymmetry between User Task and Kernel

Scratch Registers must be saved

Two Link Registers

  1. One to return from interrupt
  2. One to return from the interrupted function to whatever called it.

Helpful Features of the ICU

  1. Several places where you can read state
  2. Several places where you can block interrupt flow
  3. Trigger hardware interrupt from software

Kernel Provision for Interrupts

  1. Initialize the kernel with interrupts disabled
  2. Turn on interrupts by having user PSW with interrupts enabled
  3. Find source of interrupt
  4. Turn off source of interrupt
  5. Handle interrupt
  6. Reschedule and activate

Three Free Choices

  1. Rescheduling
  2. Volatile Data
  3. Re-enabling interrupts

The Hardware in the Trains Lab


Interrupt Control Unit (ICU)

All input signals are

Base addresses

Basic Operation

VIC powers up with



  1. leave protection off
  2. enable in VICxIntEnable when you are ready to handle the interrupt

On an interrupt

  1. Read VICxIRQStatus
  2. Choose which interrupt you wish to handle
  3. Clear the interrupt source in the device

For debugging

  1. Use VICxSoftInt and VICxSoftIntClear to turn interrupt sources off and on in software

Hardware Definitions

Registers for Basic Operation
Register Name Offset R/W Description
VICxIRQStatus 0x00 RO One bit for each interrupt source

1 if interrupt is asserted and not masked

VICxFIQStatus 0x04 RO As above for FIQ
VICxRawIntr 0x08 RO As above but not masked
VICxIntSelect 0x0c R/W 0: IRQ, 1: FIQ
VICxIntEnable 0x10 R/W 0: Masked, 1: Enabled
VICxIntEnClear 0x14 WO Clears bits in VICxIntEnable
VICxSoftInt 0x18 R/W Asserts interrupt from software
VICxSoftIntClear 0x1c WO Clears interrupt from software
VICxProtection 0x20 R/W Bit 0 enables protection from user mode access
VICxVectAddr 0x30 R/W Enables priority hardware

See documentation.

Vectored Operation



  1. Write kernel entry point into VICxDefVectAddr
  2. If desired write special entry point into VICxVectAddry
  3. When ready to accept interrupts write source and enable into VICxVectCntly

When an interrupt occurs

  1. Read VICxVectAddr to find address
  2. Move result to PC
  3. When service is complete write VICxVectAddr to start priority hardware
Register Name Offset R/W Description
VICxVectAddr 0x030 R/W Read: address of vector for highest priority interrupt

Write: service complete, enable priority hardware

VICxDefVectAddr 0x034 R/W Default vector address
VICxVectAddry 0x100+4y R/W Vector address for interrupt y
VICxVectCntly 0x200+4y R/W Control register for interrupt y

Bit[0-4]: interrupt source for interrupt y

Bit[5]: enable vectored interrupt y

Return to: