CS452 - Real-Time Programming - Spring 2009
Lecture 14 - ARM Interrupts
Practical Detail
ARM Interrupts
Philosophy
Four Interrupt Handling Methods
Nonnested
Nested
- multiple interrupts without priority
Prioritized
- Re-entrant
- Hardware
- Software
- Direct
- Grouped
Vectored
- The fastest and the nmost tricky
- Tricks
ARM Specific
Two controllers, nested
- VICINTSOURCE[0-31] to primary
- VICINTSOURCE[32-63] to secondary
- You care about
- VICINTSOURCE4: timer counter 1
- VICINTSOURCE5: timer counter 2
- VICINTSOURCE[23,24]: UART1 [receive, transmit]
- VICINTSOURCE[25,26]: UART2 [receive, transmit]
- VICINTSOURCE36: watchdog timer
- VICINTSOURCE51: timer counter 3
- VICINTSOURCE52: UART1 general
- VICINTSOURCE54: UART2 general
Registers at
- primary: 0x800b0000
- secondary: 0x800c0000
47 registers per controller
- 11: chip control
- 16: vector addresses
- 16: vector control
- 4: chip id
Priority
- FIQ-configured interrupts (not vectored)
- IRQ-configured vecored interrupts
- IRQ-configured non-vectored interrupts
Useful Tricks
Software Interrupt
Making programming easier
- SWI,
- VICxSoftInt & VICxSoftIntClear
HALT versus Idle Task
What do you do when there are no tasks to run?
- Idle task
- diagnose system
- search for ETI
- HALT
- save power (battery)
- provided through System Controller Co-processor
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