CS452 - Real-Time Programming - Spring 2011

Lecture 29 - Power On

Pubilic Service Announcement

  1. UI is hard
  2. Build in increments. Save last^H^H^H^Hevery working version!!
  3. Reservation system needs to be tunable. Making this work robustly will be time consuming.
  4. Modularity is good; distributed control is good; many tasks, but not too many, is good;

Power On

When you turn on the power or press the reset button, what happens before you see the RedBoot> prompt?

This is not determined by the instruction set architecture (ISA).

What happens before that, and what appears at 0x00000000 is determined by the design of the system surrounding the CPU on the chip.

There are two pretty hard resets that can occur.

  1. Turning on the power
  2. Pressing the reset button

(Jumping to 0x00000000 is a much softer reset.)

Asserting either of the input reset pin on the SoC, asserts the output reset pin on the SoC.

Negating the reset input starts the boot sequence, with the SoC in its reset state. Ten hardware inputs determine how the SoC boots

TS-7200 is set up for internal pre-boot with source from the flash on the 32-bit AHB

The AHB bus has all the important high-speed components

Initial state

  1. DRAM controller not initialized
  2. Flash controller not initialized
  3. MMU flat on power up, but might be screwed up on reset

In the AHB registers is a 16K block of ROM from 0x80090000 to 0x80093fff

There is almost no context

Pre-pre-boot Sequence

  1. Jump to 0x80090018.
  2. Turn on LEDs
  3. Make the CPU completely vanilla. E.g.,
  4. Turn off watchdog timer
  5. Acquire boot state
  6. Configure external clocks (needed for serial boot)
  7. Using boot state configure

    These are configured with very conservative parameters

  8. Clear boot mode `memory map'
  9. Acquire configuration inputs
  10. Switch
  11. In the first two cases the 2048 bytes contains a memory test followed by a loader.

Pre-boot Sequence

This code knows all about the EP9302, and all about the TS7200.

  1. Sets up a stack in the ethernet buffer
  2. Sets the CPSR to a vanilla state: no interrupts, svc mode
  3. Copies 260 words of code from flash to the ethernet buffer
  4. Initializes memory controllers for the memory it has
  5. Configures GPIO.
  6. Turns off the watchdog timer
  7. Sets up the appropriate serial port for a monitor


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