CS452 - Real-Time Programming - Spring 2012

Lecture 11 - Hardware Interrupts

Public Service Annoucements

  1. Next week's classes
  2. Assignment 2


What is a server?

How are servers implemented?

Name Server

Why Do We Need a Name Server

Names constant across applications & executions interface Associated with a set of services (an API)
Task Ids vary across applications & executions implementation Associated with a particular set of instructions and data (an execution)

Possible to have multiple names per task, but

Name Server Implementation

Choose whether to block or Reply.

Hardware Interrupts

What is a Hardware Interrupt?

In the CPU

  1. Test interrupt signal before fetching the next instruction
  2. If asserted, change mode to IRQ
  3. Disable interrupt in CPSR
  4. Execute instruction at 0x18

In the Interrupt Control Unit (ICU)

In the Peripheral Hardware

When two interrupts are present

May have been two present when interrupt processing started

May have occurred since interrupt processing started

What happens next?

  1. Kernel executes with interrupts disabled
  2. Context switch into user task turns on interrupts
  3. Before fetching the first user task instruction test interrupt signal
  4. If asserted, re-initiate interrupt processing

Context Switches for Interrupts

Difference from Software Interrupts

It is impossible to predict where they occur

Assymmetry between User Task and Kernel

Scratch Registers must be saved

Two Link Registers

  1. One to return from interrupt
  2. One to move to the caller's stack frame

Helpful Features of the ICU

  1. Several places where you can read state
  2. Several places where you can block interrupt flow
  3. Trigger hardware interrupt from software

The Hardware in the Trains Lab

32-bit Timer

Base address: 0x80810080

Three registers:

Offset Function R/W Bits Comments
0x0 Timer3Load R/W 32: <Load/Reload Value>
0x4 Timer3Value R 32:<Current value> Set when Load is written,
even when counting
0x8 Timer3Control R/W 3:xxx<CLKSEL>xx<MODE><ENABLE> <CLKSEL>: 0, 2KHz clock; 1, 508KHz
<MODE>: 1, count continuously; 0, count once
<ENABLE>: Clock turned on
0xc Timer3Clear W 32: Writing anything clears the interrupt

Interrupt Control Unit (ICU)

The actual device is the ARM PL190

The logic in this design is completely asynchronous, so it functions when the CPU clock is turned off.

All input signals are

Base addresses

Basic Operation

VIC powers up with



  1. leave protection off
  2. enable in VICxIntEnable when you are ready to handle the interrupt

On an interrupt

  1. Read VICxIRQStatus
  2. Choose which interrupt you wish to handle
  3. Clear the interrupt source in the device

For debugging

  1. Use VICxSoftInt and VICxSoftIntClear to turn interrupt sources off and on in software

Hardware Definitions

Registers for Basic Operation
Register Name Offset R/W Description
VICxIRQStatus 0x00 RO One bit for each interrupt source

1 if interrupt is asserted and enabled

VICxFIQStatus 0x04 RO As above for FIQ
VICxRawIntr 0x08 RO As above but not masked
VICxIntSelect 0x0c R/W 0: IRQ, 1: FIQ
VICxIntEnable 0x10 R/W 0: Masked, 1: Enabled
VICxIntEnClear 0x14 WO Clears bits in VICxIntEnable
VICxSoftInt 0x18 R/W Asserts interrupt from software
VICxSoftIntClear 0x1c WO Clears interrupt from software
VICxProtection 0x20 R/W Bit 0 enables protection from user mode access
VICxVectAddr 0x30 R/W Enables priority hardware

See documentation.

Helpful Features of the ICU

  1. Several places where you can read state
  2. Several places where you can block interrupt flow
  3. Trigger hardware interrupt from softwareonce
    1. What makes interrupts hard is that you are doing two semi-hard things at once
      • Making the hardware produce the interrupt
      • Responding to the interrupt
    2. Software interrupt generation allows you to separate them in developing/debugging

Non-vectored Operation


  1. Enable interrupt in device
  2. Enable interrupt in ICU
  3. Enable interrupt in CPU, usually by MOVS

Interrupt occurs

  1. AND of IRQ and NOT( IRQ disabled ) is checked before each instruction fetch.
  2. If set IRQ exception is taken in place of next instruction fetch.
  3. Context switch into kernel

    Context switch novelties

    Difference from Software Interrupts

  4. Turn off interrupt in device

You are now ready to process the interrupt in the kernel

Vectored Operation



  1. Write kernel entry point into VICxDefVectAddr
  2. If desired write special entry point into VICxVectAddry
  3. When ready to accept interrupts write source and enable into VICxVectCntl

When an interrupt occurs

  1. Read VICxVectAddr to find address
  2. Move result to PC
  3. When service is complete write VICxVectAddr to rerun priority hardware
Register Name Offset R/W Description
VICxVectAddr 0x030 R/W Read: address of vector for highest priority interrupt

Write: service complete, enable priority hardware

VICxDefVectAddr 0x034 R/W Default vector address
VICxVectAddry 0x100+4y R/W Vector address for interrupt y
VICxVectCntly 0x200+4y R/W Control register for interrupt y

Bit[0-4]: interrupt source for interrupt y

Bit[5]: enable vectored interrupt y

Return to: