CS452 - Real-Time Programming - Spring 2012

Lecture 30 - Power On

Public Service Annoucements

  1. Final exam date: 9.00 August 7 to 11.30 August 9

Power On

When you turn on the power or press the reset button, what happens before you see the RedBoot> prompt?

This is not determined by the instruction set architecture (ISA).

What happens before that, and what appears at 0x00000000 is determined by the design of the system surrounding the CPU on the chip.

There are two pretty hard resets that can occur.

  1. Turning on the power
  2. Pressing the reset button

(Jumping to 0x00000000 is a much softer reset.)

Asserting the reset input of the SoC, asserts the reset output of the SoC.

Negating the reset input starts the boot sequence, with the SoC in its reset state. Ten hardware inputs determine how the SoC boots

These inputs allow the designer of the board hosting the SoC to determine enough characteristics of the boot state that it can be used for many applications

TS-7200 is set up for internal pre-boot with source from the flash on the 32-bit AHB

The AHB bus has all the important high-speed components

Initial state


The following things, which are contolled through the system control co-processor, are determined by the CPU architecture. They must be independent of the stuff added by Cirrus

  1. MMU flat, but might be different on soft reset
  2. Caches disabled
  3. Slow bus clock
  4. Interrupts disabled
  5. Little-endian memory system
  6. No access to MMU registers
  7. Normal exception registers


The following things, which are described in the EP9302 documentation, are properties of hardware Cirrus added. They are independent of how Technologic configured the chip when they designed the TS7200.

  1. DRAM controller(s) not initialized
  2. Flash controller(s) not initialized
  3. All I/O devices in reset state. (They receive hardware reset inputs from the CPU.)
  4. Memory map in boot mode


The following things, which are described in the Technologic documentation, manual & circuit diagram, are properties of the TS7200

  1. Boot control bits, set to normal boot, 32-bit bus width, sychronous boot device, internal, watchdog timer disabled.
  2. Physical memory map
  3. In the AHB registers is a 16K block of ROM from 0x80090000 to 0x80093fff

Pre-pre-boot Sequence

  1. Jump to 0x80090018.
  2. Turn on LEDs
  3. Make the CPU completely vanilla. E.g.,
  4. Turn off watchdog timer
  5. Acquire boot state
  6. Configure external clocks (needed for serial boot)
  7. Acquire boot state configuration inputs
  8. Using boot state configure

    These are configured with very conservative parameters

  9. Clear boot mode `memory map'
  10. Toggle LEDs
  11. Switch
  12. In the first two cases the 2048 bytes contains a memory test followed by a loader.

Pre-boot Sequence

This code knows all about the EP9302, and all about the TS7200.

  1. Sets up a stack in the ethernet buffer
  2. Sets the CPSR to a vanilla state: no interrupts, svc mode
  3. Copies 260 words of code from flash to the ethernet buffer
  4. Initializes memory controllers for the memory it has
  5. Configures GPIO.
  6. Turns off the watchdog timer
  7. Sets up the appropriate serial port for a monitor

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