CS452 - Real-Time Programming - Winter 2018
Lecture 29 - Power On.
Public Service Annoucements
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Final Demo, Thursday/Friday, 5/6 April.
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The exam will start at 09.00, April 22, 2018 and finish at 11.30,
23 April 2018.
What Happens First when you turn on the Power Switch
The Hardware
The hardware is constructed in four layers: the processor (CPU),
the System on Chip (SoC), the circuit board (PCB) and connectors,
and the outside world. The designer of each layer knows about
the layers below it, and expects something from the layers above
it.
ARM processor
The CPU is a wire list, containing
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a list of electronic components, transistors, resistors,
capacitors, and
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a description of which input is connected to which output.
In practice the wire list may be a set of masks.
It knows only about itself, which means the CPU architecture,
which includes such things as executing the instruction at address
zero when the reset input is negated.
It expects
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a clock signal,
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memory, including a set of instructions and temporary data
storage,
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regulated power, and
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inputs that activate exceptions.
These expectations are provided by the Cirrus SoC.
The Cirrus SoC
The Cirrus SoC is a silicon chip that includes
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an implementation of the CPU,
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an implementation of memory interfaces,
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implementations of I/O devices, including inputs that
activate exceptions,
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clock dividers to provide clocks for the busses and the I/O
devices,
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wires connecting all these devices, which include system
busses and power distribution,
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enough static memory to provide temporary storage during
the pre-pre-boot sequence, and
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enough read-only memory to provide instructions for the
pre-pre-boot sequence.
Implementation means implemented as a set of masks through which
various impurities will be deposited to turn pure silicon into
transistors and other electronic components. All this stuff is
called mask-programmed because it is cast in stone before the
first chip is manufactured.
The pre-pre-boot instructions are located on the advanced high-speed
bus (AHB) from 0x80090000 to 0x80093fff.
The SoC knows about
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the architecture of the CPU, and
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itself.
The SoC expects
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regulated power,
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a master clock signal,
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memory, static, dynamic and/or flash,
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LEDs for the earliest I/O,
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adapters for I/O devices, such as line drivers and receivers, and
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settings for five bits of configuration input.
These expectations are provided by the Technologic circuit board.
The Technologic Circuit Board and Case
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Power supply,
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the master clock,
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Line drivers for I/O
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Headers for I/O
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LEDs: one red, one green
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Jumpers to set configuration
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DRAM - 32 Mbytes
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Actually set up for 64 Mbytes.
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26 bits of address needed to address it all: 13 bits for row, 13
bits for column.
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What happens when the memory doesn't use an address bit? That bit
is ignored: there are gaps in the memory.
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Actual memory is broken into 4 Mbyte (22 bit) blocks, with nothing
between them. Bit 23 of the address is always 0.
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FLASH memory, which holds the instructions for the pre-boot
code that starts RedBoot, bringing you to the RedBoot prompt.
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UART3 implemented by PLA.
Turing on the Power
When you turn on the power or press the reset button, what happens
before you see the RedBoot>
prompt? Turning on the power causes the power
controller to
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assert the reset input to the CPU, and
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turn on the master clock.
This is not determined by the instruction set architecture (ISA).
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The power supply asserts it, holding the assertion long enough that
everything on the board has stable power.
Asserting the reset input of the SoC, asserts the reset output
of the SoC.
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The output reset goes everywhere and resets everything with
a power on reset.
Negating the reset input starts the boot sequence, with the SoC
in its reset state. Ten hardware inputs determine how the SoC
boots
- internal/external
- pre-boot source
- watchdog state
- bus width of pre-boot and pre-pre-boot
These inputs allow the designer of the board hosting the SoC to determine
enough characteristics of the boot state that it can be used for many
applications
TS-7200 is set up for internal pre-boot with source from the flash on the
32-bit AHB
The AHB bus has all the important high-speed components
- memory (program and graphics)
- ethernet controller
- USB controller, and
- 16Kbytes of mask-programmed ROM at
0x80090000
Initial state
ARM
The following things, which are contolled through the system control
co-processor, are determined by the CPU architecture. They must be
independent of the stuff added by Cirrus
- MMU flat, but might be different on soft reset
- Caches disabled
- Slow bus clock
- Interrupts disabled
- Little-endian memory system
- No access to MMU registers
- Normal exception registers
Cirrus
The following things, which are described in the EP9302 documentation, are
properties of hardware Cirrus added. They are independent of how Technologic
configured the chip when they designed the TS7200.
- DRAM controller(s) not initialized
- Flash controller(s) not initialized
- All I/O devices in reset state. (They receive hardware reset inputs
from the CPU.)
- Memory map in boot mode
Technologic
The following things, which are described in the Technologic
documentation, manual & circuit diagram, are properties of the TS7200
- Boot control bits, set to normal boot, 32-bit bus width, sychronous
boot device, internal, watchdog timer disabled.
- Physical memory map
- In the AHB registers is a 16K block of ROM from
0x80090000
to 0x80093fff
- Initially, it is mapped to the entire memory space at 16K
intervals.
- Chip select, and how addressing occurs.
- Chip select of this block is
0x8009[00XXb]XXX
- Chip select has two parts
- I/O chip select:
0x8XXXXXXX
- AHB chip select:
0xY00XXXXX
- ROM chip select:
0xYYY9[00XXb]XXX
- The first instruction executed is the one that you find at
0x80090000
Pre-pre-boot Sequence
- Jump to
0x80090018.
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Remap memory.
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Turn on red LED; turn off green LED
- Make the CPU completely vanilla. E.g.,
- no caches, physical memory map,
- Turn off watchdog timer
- Acquire boot state
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Configure the clocks to run from external source (needed for serial boot)
- Acquire boot state configuration inputs
- These are input pins on the EP9302, the state of which is
determined by the TS7200.
- A couple are user-controllable via jumpers
- They are the only thing the EP9302 knows about the outside
world
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Using the memory width given in the boot state register
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Initialize Flash and SDRAM memory controllers for slowest
possible access.
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Give the memory a minimal test.
- Toggle LEDs
- Switch
- Serial boot on UART1
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Initializa UART1
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Output ">"
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Check for SURC or CRUS in first four bytes
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Read 2048 bytes from UART1 to the ethernet buffer
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Output "<" to ACK bytes
Turn on green LED
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Jump to the start of the ethernet buffer and start the pre-boot.
Boot from ROM outside SoC
- Assert ROM chip selects looking for CRUS
- When found read 2048 bytes from the ROM to ethernet buffer
- Jump to the start of the ethernet buffer
Boot from flash
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Look for SURC or CRUS at possible flash start locations
(ten in all)
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When found jump to start location plus
0x4 (account
for CRUS)
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If not found
- load infinite loop into ethernet buffer
- flash green LED forever
In the first two cases the 2048 bytes contains a memory test followed
by a loader.
Pre-boot Sequence
This code, provided by Technologic, knows all about the EP9302,
and all about the TS7200.
- Sets up a stack in the ethernet buffer
- Sets the CPSR to a vanilla state: no interrupts, svc mode
- Copies 260 words of code from flash to the ethernet buffer
- Initializes memory controllers for the memory it has
- Configures GPIO.
- Turns off the watchdog timer
- Sets up the appropriate serial port for a monitor
- Code in the ethernet buffer loads RedBoot
- Jump to the start of RedBoot
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