Two inputs
Output Q
S R P Q
F F T F
F T
T F F T
F T T F
T T F F
On S: F -> T sets Q to T, P to F
On T: F -> T resets Q to F, P to T
In other words, by briefly, whatever that means in practice, asserting S or R you put the SR flip-flop into a state in which it remains until next set or reset. That is, it remembers what happened most recently to it.
Consider the transition from (SR)=(TT) to (SR)=(FF)
Why is a clock important?
What kind of chip provides a clock?
Why is the clock difficult to implement?
We will now modify the flip-flop so that it samples its input when it gets a clock input
Two inputs:
Outputs: Q Qbar
Clock high: output follows input
Clock low: output stays constant
The latch samples the input on the high to low clock transition, then holds it
Where might you use a latch?
Do the exercises on pp. 13-14 of the notes.
Two D-latches in a master-slave configuration.
Arrays of D flip-flops all clocked by the same clock.
Just a collection of registers
Read-write logic
A bus, by definition, can be driven by more than one source. How can this be done?
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