CS251 - Computer Organization and Design - Spring 2008
Lecture 8 - Finite state machines
Practical Details
- Assignment 1.
- Assignment 2.
- Next Friday.
State
SRAM
Based on the D latch with three state output
Write:
- address assert AND write strobe on clock
- data puton D
Read:
- address assert on E
- data read from Q
Two bits of address, two bits of data.
SRAM is used for special (low power, cache, etc) memory because it is
- expensive, because big on the die,
- fast, because it is refresh-free
Controllers Based on Finite State Machines.
Ingredients
- Clock
- Register to hold state, sampled by clock
- Inputs
- Outputs
- Logic to compute next state and outputs from this state and inputs.
Controllers use the simplest way of addressing memory
- a dedicated line on the bus for every bit.
- which potentially requires a very large number of bits
More scalable, and more complex ways of addressing use binary-coded
addresses with a common data bus using
- decoders
- RAS, CAS addressing
- multiplexors
- 3-state output drivers
DRAM
Error in the notes. Page 18, bottom, should read.
- Transistor is a switch
- When the word line is asserted the switch is closed.
- Otherwise it's open.
- Closed switch transfers charge.
- Bit line transfers charge to capacitor on write
- Capacitor transfers charge to bit line on read
- Bit line is half way between high and low.
- Open switch
- Holds charge on capacitor
- Keeps impedance of connection to bit line high
DRAM Refresh
- Charge slowly drains away, weakening the signal.
- Read, which weakens state further
- Rewrite, which makes it new again.
Typical to refresh once every few milliseconds
- Refresh occurs part of a memory chip at a time, and that part is not
available for reading or writing while the refresh takes place.
Error in notes. Page 19, line starting `If capacitors ...' should read
- Capacitors hold charge well-enough that they need to be refreshed every
few milliseconds, say 4 milliseconds to be concrete.
- Refresh takes less than 20 to 50 microseconds
- Therefore the memory is unavailable for about 2% of the time.
SSRAM and SDRAM
The first `S' stands for synchronized.
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