CS251 - Computer Organization and Design - Spring 2008

Lecture 15 - Data Flow

Practical Details

1. Read 5.1 to 5.4, C.2

Instruction Execution Components

The more you can keep them separate the more you can

• parallelize
• pipeline

Instruction Fetch

Sequence

1. Signal to fetch
2. Read cycle to instruction memory with PC as address
3. Increment PC by 4 (combinational logic)

Often there is a FIFO

• What about branching?

Datapaths

1. PC to memory
2. PC to adder
3. Adder to PC
4. Instruction to next stage

Decode Instruction and route the parts accordingly

Instruction Types

1. Register instructions
2. Memory instructions
3. Branch instructions

Register (R-type) Instructions

Arithmetic, logical

• Need two arguments, one destination, all are data

Details

1. Argument parts of instruction select read and write registers
2. ALU part of instruction selects operation of ALU
3. Register file has two read outputs determined by two selector
4. Register file has one write input, determined by a third selector

Sequence

1. Read arguments of instruction put register values on path to ALU input
2. ALU part of instruction selects the combinational logic function to be applied
3. Result appears on ALU output
4. ALU output written to register selected by argument

Datapaths

1. Instruction to register file
2. Instruction to ALU
3. Register file to ALU input
4. ALU output to register file

Memory Instructions

Register to/from memory

• need data, address
• data in register
• address = register value plus offset

Details

1. Offset in last 16 bits of instruction

Sequence

1. Get arguments from registers
   • address register to ALU
   • data register to write port of memory
2. Add offset to address is ALU, send result to memory address
3. Read/Write
   • write pushes data into write port
   • read flushes data out of read port
4. If read data latched into register

Datapaths

1. Instruction to register file
2. Instruction to ALU
3. Register file to memory write port
4. Register file to ALU
5. ALU to memory address
6. Memory read port to register file

Branch/Jump Instructions

Branch

Will change program counter if condition is true

Needs

1. two registers to compare data

   one address to branch to: in the code, Why?

Details

• branch target in low 16 bits of instructions
• but target can be up to 2^18

Sequence

1. Instruction arguments to register file
2. Branch target to sign extender to shifter
3. Data from register file to ALU
4. ALU calculates result
5. Shifted output and PC + 4 to adder
6. Target on output of adder

Datapaths

1. Instruction to register file
2. Instruction to sign extender to shifter to adder
3. PC + 4 to adder
4. Register file to ALU
5. Adder and ALU to branch control logic

Put It All Together

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• Bill Cowan's lecture notes for CS251 in W08
• Bill Cowan's Winter 2008 CS251 page
• Bill Cowan's CS251 page
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