CS251 - Computer Organization and Design - Spring 2008

Lecture 17 - Data Flow

Practical Details

1. Assignment 4
2. Friday's class

Instruction Execution Components

Branch/Jump Instructions

Branch

Will change program counter if condition is true

Needs

1. two registers to compare data

   one address to branch to: in the code, Why?

Details

• branch target in low 16 bits of instructions
• but target can be up to 2^18

Sequence

1. Instruction arguments to register file
   • read1
   • read2
2. Branch target to sign extender to shifter
3. Data from register file to ALU
4. ALU calculates result
5. Shifted output and PC + 4 to adder
6. Target on output of adder

Datapaths

1. Instruction to register file
2. Instruction to sign extender to shifter to adder
3. PC + 4 to adder
4. Register file to ALU
5. Adder and ALU to branch control logic

Put It All Together

Instruction fetch

1. PC
2. Instruction memory
3. Adder: no longer goes straight to PC, but is output (branch)

Control: none

R-type instruction

1. Registers
   • read1 -> ALU
   • read2 -> ALU
   • write: needs a MUX because sometimes the second one comes here (load)
2. ALU

Control signals:

1. Clock
2. Regwrite
3. ALU operation select (3)

I-type instructions

Load/store

1. Registers
   • read1 -> ALU for address calculation
   • read2 -> memory with data to be written
   • write -> needs a MUX, might be
     • third register field (R-inst)
     • second register field (I-inst)
2. Sign extender
3. ALU: combines read1 and sign-extended immediate
4. Data memory: needs a MUX on output
   • could be load
   • could be ALU output

Control signals

1. Regwrite
2. ALUctl (3)
3. MemRead
4. MemWrite
5. MemToReg

Conditional branch

1. Registers
   • read1 -> ALU
   • read2 -> ALU
2. ALU:
   • zero output
   • needs a MUX on input
     • could be sign extended instruction for load/store
     • could be read2 for r-type
3. Sign extender:
4. Shifter
5. Adder: MUX needed on output

Control signals

1. ALUctl
2. PCSrc
3. ALUSrc

Control Logic

Highest six bits of instruction is opcode

• For opcode 0, lowest six bits select function

Control logic needs to accept opcode (26:31) and function (0:5)

• and output all the control signals

Split into two stages

1. From opcode only generate all control signals except ALUctl, plus ALUop
2. From ALUop plus function generate ALUctl

Climax

The CPU plus memory is just a finite state machine, albeit a complex one.

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