CS251 - Computer Organization and Design - Spring 2008

Lecture 19 - Execution Control

Practical Details

1. Assignment 5
2. Mid-term

Instruction Execution Components

Put It All Together

Instruction fetch

1. PC
2. Instruction memory
3. Adder: no longer goes straight to PC, but is output (branch)

Control: none

R-type instruction

1. Registers
   • read1 -> ALU
   • read2 -> ALU
   • write: needs a MUX because sometimes the second one comes here (load)
2. ALU

Control signals:

1. Clock
2. Regwrite
3. ALU operation select (3)

I-type instructions

Load/store

1. Registers
   • read1 -> ALU for address calculation
   • read2 -> memory with data to be written
   • write -> needs a MUX, might be
     • third register field (R-inst)
     • second register field (I-inst)
2. Sign extender
3. ALU: combines read1 and sign-extended immediate
4. Data memory: needs a MUX on output
   • could be load
   • could be ALU output

Control signals

1. Regwrite
2. ALUctl (3)
3. MemRead
4. MemWrite
5. MemToReg

Conditional branch

1. Registers
   • read1 -> ALU
   • read2 -> ALU
2. ALU:
   • zero output
   • needs a MUX on input
     • could be sign extended instruction for load/store
     • could be read2 for r-type
3. Sign extender:
4. Shifter
5. Adder: MUX needed on output

Control signals

1. ALUctl
2. PCSrc
3. ALUSrc

Control Logic

Highest six bits of instruction is opcode

• For opcode 0, lowest six bits select function

Control logic needs to accept opcode (26:31) and function (0:5)

• and output all the control signals

Split into two stages

1. From opcode only generate all control signals except ALUctl, plus ALUop
2. From ALUop plus function generate ALUctl

Signals to generate

Opcodes

ALUCtl

Timing

Suppose

• memory units 200 picoseconds
• ALUs 100 ps
• register files 50 ps

Then for R-type instructions

• Longest path (?)
  1. inst fetch : 200 ps (really?)
  2. argument values : 50 ps
  3. ALU : 100 ps
  4. result write : 50 ps
  5. total : 400 ps (200 ps ?)
• Other paths

But for loads

• Longest path (?)
  1. argument values : 50 ps
  2. ALU : 100 ps
  3. result read : 200 ps
  4. result write : 50 ps
  5. inst fetch : 200 ps (really ?)
  6. total : 600 ps (400 ps ?)

And for conditional branches

• Longest path
  1. argument values : 50 ps
  2. ALU: 100 ps
  3. inst fetch : 200 ps
  4. total : 350 ps

  Possible competitor

  1. inst fetch : 200ps
  2. everything else done before start of clock

Climax

The CPU plus memory is just a finite state machine, albeit a complex one.

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