CS251 - Computer Organization and Design - Spring 2008

Lecture 22 - Intreoduction to Multiple Cycle Designs

Practical Details

1. Exam results
   • mean 40.4 (67%)
   • std dev 10.3 (17%)
   • 25% point 33.5 (56%)
   • median 44.3 (74%)
   • 75% point 48 (80%)
2. Assignment this week
   • Add a shift instruction: srl rd, rt, shamt -- | 000000 | rs | rt | rd | shamt (5 bits) | 000010 |

Single Cycle Weaknesses

Control Logic

Seems pretty ad hoc.

• See below

Extensibility

See above

Timing

Different cycles take different amounts of time

• Clock can be no faster than the slowest

Pipelining

Phases of instruction execution

1. Instruction fetch & decode
2. Operand values
3. Result calculation
4. Result writeback

We would like to get these separated from one another,

• which means storing state between phases

And yet,

The most popular processor architecture in the world is a single cycle one

Which brings up a MIPS oddity

No condition codes

• What are condition codes
  1. N - negative: bit 31 of most recent result
  2. Z - zero: NAND of all bits of result
  3. C - carry:
     • addition: carry out of MSB (unsigned overflow)
     • subtraction: borrow in MSB (unsigned underflow)
     • shift: last bit shifted out
     • otherwise unchanged
  4. V - overflow:
     • addition/subtraction: overflow in TCI
     • otherwise unchanged

MIPS uses the set instruction followed by conditional branch

Multicycle Execution

Separating the phases

Instruction Fetch

Store instruction in register

• You can now put a different address on the address lines
• The only restriction is that you can't latch it into the instruction register until you ar finished with the ocntents of the instruction register
• You can also change the program counter
  • probably using the ALU, which is not yet being used by any of your arguments
  • Latch the new program counter into the PC-register at the same time you latch the instructiuon into the instruction register.

Increment PC using ALU

Evaluating Operands

Put operands into registers, which are input to

• ALU
• Memory

Control Logic

Highest six bits of instruction is opcode

• For opcode 0, lowest six bits select function

Control logic needs to accept opcode (26:31) and function (0:5)

• and output all the control signals

Split into two stages

1. From opcode only generate all control signals except ALUctl, plus ALUop
2. From ALUop plus function generate ALUctl

Signals to generate

Opcodes

ALUCtl

Timing

Suppose

• memory units 200 picoseconds
• ALUs 100 ps
• register files 50 ps

Then for R-type instructions

• Longest path (?)
  1. inst fetch : 200 ps (really?)
  2. argument values : 50 ps
  3. ALU : 100 ps
  4. result write : 50 ps
  5. total : 400 ps (200 ps ?)
• Other paths

But for loads

• Longest path (?)
  1. argument values : 50 ps
  2. ALU : 100 ps
  3. result read : 200 ps
  4. result write : 50 ps
  5. inst fetch : 200 ps (really ?)
  6. total : 600 ps (400 ps ?)

And for conditional branches

• Longest path
  1. argument values : 50 ps
  2. ALU: 100 ps
  3. inst fetch : 200 ps
  4. total : 350 ps

  Possible competitor

  1. inst fetch : 200ps
  2. everything else done before start of clock

Climax

The CPU plus memory is just a finite state machine, albeit a complex one.

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