CS251 - Computer Organization and Design - Spring 2008
Lecture 27 - Pipelining
Practical Details
- Assignment 6
Exceptions
The Basic Idea
Sometimes, we hope not too often, something unusual happens
- internal: fault in instruction execution
- external: something needs to be done
- a packet arrived
- I/O operation completed
- etc.
Once upon a time:
- 1 was an exception
- 2 was an interrupt
68000 supposed they were the same thing
- now they are both exceptions
On an exception a complex collection of software operations occurs
- State of runing task is saved
- OS runs code to handle exception
- Normal operation is resumed
What does the processor do? a pseudoinstruction or a complex
instruction
- saves minimum of state (PC, SP)
- transfers control to new PC, usually read from memory
Concrete example
- old PC in special register
- memory cycle to magic address
- data into PC.
Pipelining
We made each instruction into a sequence of phases
- instruction fetch, uses
- instruction decode and operand generation, uses
- register file
- ALU
- decode logic
- execute: split across instruction type
- R-type result computation
- M-type: address computation
- B-type: condition computation
uses
- memory access: M-type only, uses
- writeback to register: R-type, M-type, uses
For good pipelining
Make all phases of instruction execution the same length
- One instruction length
- exactly one memory access
- Few instruction formats
- fast instruction decode for operand access
- Restricted memory access
- at most twice (intruction once, data once) per instruction
Comparison
|
Single-cycle |
Multi-cycle |
Pipelined |
| Instruction types |
3 |
3 |
3 |
| Instruction lengths |
1 slow cycle |
3,4,5 fast cycles |
5 fast cycles |
| Instruction issue |
1 per cycle |
1 per weighted average |
1 per cycle |
| ALUs |
2 slow, 1 fast |
1 fast |
3 fast |
| Memories |
2 |
1 |
2 |
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Hazards
Any condition that blocks the flow of instruction through the pipeline
Structural
Hardware prevents two phases from overlapping
- e.g. instruction fetch, memory access for single memory
Control
Don't know PC in time for next instruction fetch
Data
Result of one instruction needed in the next one.
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