CS251 - Computer Organization and Design - Spring 2008
Lecture 28 - Hazards
Practical Details
- Assignment 7
- Read Chapter 6 in the textbook
Pipelining
We made each instruction into a sequence of phases
- instruction fetch, uses
- instruction decode and operand generation, uses
- register file
- ALU
- decode logic
- execute: split across instruction type
- R-type result computation
- M-type: address computation
- B-type: condition computation
uses
- memory access: M-type only, uses
- writeback to register: R-type, M-type, uses
For good pipelining
Make all phases of instruction execution the same length
- One instruction length
- exactly one memory access
- Few instruction formats
- fast instruction decode for operand access
- Restricted memory access
- at most twice (intruction once, data once) per instruction
Comparison
|
Single-cycle |
Multi-cycle |
Pipelined |
| Instruction types |
3 |
3 |
3 |
| Instruction lengths |
1 slow cycle |
3,4,5 fast cycles |
5 fast cycles |
| Instruction issue |
1 per cycle |
1 per weighted average |
1 per cycle |
| ALUs |
2 slow, 1 fast |
1 fast |
3 fast |
| Memories |
2 |
1 |
2 |
Read chapter 6.2, looking carefully at each diagram.
Control signals
The idea here is simple in principle, but complicated in practice.
If there are five instructions in the pipeline we need five sets of
control signals, one set for each instruction.
- The instruction in phase 1 needs to get phase 1 control signals
- Other instructions are generating phase 2 to 5 control signals
- The phase 2-5 control signals need to be kept away from the hardware
being used for phase 1
Hazards
Any condition that blocks the flow of instruction through the pipeline
Structural Hazards
Hardware prevents two phases from overlapping
- e.g. instruction fetch, memory access for single memory
- solution: extra hardware
This means that we are working with the hardware of the single-cycle
processor
- one ALU, two adders
- separate instruction and data memory
Draw synchronization blocks where phases end
- the hardware components may be single-cycle, but control is
multi-cycle.
| Drawing pipelines |
| 1. When we draw instruction execution in a pipeline the emphasis is
on the resources being used. Thus, we draw the resource being used in
each pipeline step.
2. You should notice something fishy: the register file is used in
the second and fifth phase of processing:
- in the second to get operands
- in the fifth to write back data.
Surely these phases cannot overlap.
3. The solution is to separate phases two and five into a early
and a late phase.
- Registers are accessed in the late part of phase 2
- Registers are accessed in the early part of phase 5.
4. In drawings the early and late phase are differentiated by
separating by drawing register use in only half the phase, as is done
for instruction memory, data memory and register file throughout
Chapter 6 of the textbook.
5. Note that the schematic registers (long horizontal rectangles)
are highlighted on the left side when they are accepting data from
the previous phase, and on the right side when they are providing
stabilized data to the next phase.
|
Control Hazards
Don't know PC in time for next instruction fetch
Possible solutions
- Stall
- PC can be known during the second phase of conditional branch
instructions.
- Skip one instruction dispatch
- Dispatch instruction calculated in the second phase of the previous
instruction
- Test is done by extra hardware that operates immediately on
register file outputs.
- Delayed branch
- Find an instruction on which the branch result does not depend
- Put it into the spare instruction slot.
- Otherwise put a NOP there, which is the same as a stall..
- Static branch prediction
- Assume branch not taken
- Start the next instruction(s)
- If the branch is taken,
- Stop the instruction(s) before writeback
- Dynamic branch prediction
- One-bit prediction
- do what you did last time
- correct 80% of the time
- Two-bit prediction
- only change what you do if you do the opposite two times in a
row.
- correct 90% of the time.
Data Hazards
Result of one instruction needed in the next one.
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