CS251 - Computer Organization and Design - Spring 2008

Lecture 33 - Other Cache Types

Practical Details

1. Assignment 8
2. History of computing
3. Reminder: what we are doing is called direct mapping.

Examples of Cache Memories

1. One word per cache line, 16 Cache lines

Cache

Address

Circuit (p. 476)

1. Ignore access size bits
2. Use 5-2 to choose the line in the cache
3. Test 31-6 against the tag in the line
4. AND with valid to get HIT
5. Return data in line plus HIT

Comments

A very basic cache.

Easy to see how to extend to a bigger cache.

2. Longer cache lines: 16 word line, 256 lines

Cache

Address

Circuit (p. 486)

1. Ignore bits 0-1
2. Use bits 13-6 to choose the line in the cache
3. Compare bits 31-14 to the tag
4. AND the result with Valid to get HIT
5. Multiplexer selects word to return based on bits 5-2

Comments

Typical early cache technology

Cache Misses

On Read

Send memory line number to main memory (SDRAM).

SDRAM returns whole line in one transaction

• Address to DRAM, Data 0 to Cache, Data 1 to cache, etc.
• Wait until word 0 typically 40 nsec
• Then time per word much faster, 2-4 nsec.
• Reason is slow row addressing, fast column addressing

Load instruction, or instruction fetch is rerun.

• Pipeline is frozen while this takes place

On Write

Send memory line number to main memory (SDRAM).

SDRAM returns whole line in one transaction

• Address to DRAM, Data 0 to Cache, Data 1 to cache, etc.
• Wait until word 0 typically 40 nsec
• Then time per word much faster, 2-4 nsec.

Store instruction is rerun.

• Pipeline is frozen while this takes place.

Main memory is synchronized

• Write-through: two writes happen at once
  • but what if another write occurs immediately after?
  • possibly stall
  • assisted by a hardware write queue
• Write-back: don't synchronize immediately, but when the cache line leaves the cache
  • some misses are even more expensive
  • multi-processing is difficult

Possible Improvements

Obvious trade-off: the longer the lines

• the fewer misses, and

  the higher the cost of a miss

The best performance depends on locality in the code.

• the compiler can help.

Typically, cache misses slow the processor by a factor of 2.

Widen and speed up bus between main memory and cache.

Send the desired word first, then fill the rest of the line.

More than one line per set of address bits.

Other Cache Organizations

Fully Associative

Cache lines are not addressable

Memory

Address

• n1: normally 2
• n2-n1: log_2 (number of words in a line)

Circuit

1. All tags compared in parallel.
   • Results ANDed with the corresponding Valid bit to give LineHit
2. All words activated in parallel
3. All LineHits ORed to give Hit
4. If ( Hit )
   • Multiplexer addressed by location of LineHit chooses correct word
5. else
   • Processor is stalled
   • Line is chosen to remove from cache
   • Line is retrieved from next level of memory
   • Instruction is rerun

Set Associative

Effectively a set of direct mapping caches

• associative mapping between sets

Cache

Address

• n1: normally 2
• n2-n1: log_2 (number of words in a line)
• n3-n2: log_2 (number of lines in a set)

Circuit (Figure 7.17, page 503)

1. Use line number in set to choose a horizontal set of lines
2. In parallel match Line number in memory to each tag in the set
   • AND with Valid to get SetHit
3. In parallel use Word number in line to activate one word in each set
4. All SetHits ORed to get Hit
5. If (Hit) then
   • Multiplexer addressed by true SetHit selects word to return
6. Else
   • Processor is stalled
   • Line is chosen to remove fram cache
   • Line is retrieved from next level of memory
   • Instruction is rerun

New Issues

Replacement Algorithm

Usually least recently used (LRU). i.e. most dusty

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