CS452 - Real-Time Programming - Fall 2008

Lecture 15 - Serial Hardware

Questions & Comments

UART pdf

The 16550 UART

Twelve registers, but only eight addresses, differentiated by A0-A2

Five interrupt sources

0110 - Receiver line status
- cleared by read line status register
0100 - Received data available
- clear by reading input buffer
1100 - FIFO timeout
- clear by reading breceive buffer
0010 - Transmitter holding register empty
- clear by
  - reading IIR register
  - writing transmit buffer
0000 - Modem status
- clear by reading modem status register

Interrupt Control Unit

Interface between devices and CPU

found in south bridge
two addresses differentiated by A0

Description

many interrupt inputs
one interrupt output, physically connected to interrupt input of CPU
programmed at initialization
read to discover the source of the input

Hardware Interface

Interrupt output pin of device connected physically to one of the interrupt input pins of ICU

Processor Interface

Occurs during interrupt processing

CPU runs an I/O read bus cycle during interrupt processing

ICU responds with highest priority interrupt currently asserted
- ICU responds with 8-bit vector
- not necessarily the interrupt that initiated the interrupt process.
CPU then looks up vector in IRT
- installs what it finds in CS:EIP

OS Interface

Can know interrupt source from CS:EIP

first instruction sets a register

Or can read source from ICU

might be a different interrupt

Can be more than one interrupt source at the device (e.g. 16550 UART). If so,

process each one in turn by taking subsequent interrupts
removing each one as you process it

Interrupt(s) removed from device

remove interrupt from ICU
very small window in which interrupt can be lost

The 8259 ICU (PIC)

Priorities set by how the ICU is wired to the peripheral.

Low three bits of the interrupt vector are the priority.

Initialization

A0=0 and D4=1 means first initialization command

ICW1

Set all inputs to edge-triggered
Clear interrupt mask register
Status read set to IRR
D1 sets single/cascade mode
D0 indicates whether or not there will be an ICW4

ICW2

A0=1
D3-D7 set the high bits of the interrupt vector

ICW3

A0=1
Only run in cascade mode
If master Dn=1 says interrupt n comes from a slave D0 set to zero

ICW4

EOI/AEOI is what you care about most
Why?

Operation

OCW1

A0=1
Set the 8 mask bits to D0-D7

OCW2

A0=0
D7-D5 rotate priorities, send EOI
D0-D2 set priority

OCW3

A0=0, D3=1
D5, D6 set mask mode
D2 poll command?
D1 pay attention to D0
D0 which register to be read

To read status

IRR, ISR: read following OCW3
IMR: read with A0=1 following OCW1

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