CS452 - Real-Time Programming - Fall 2010

Lecture 13 - Hardware Interrupts

Pubilic Service Announcements

  1. AwaitEvent
  2. Marked Assignments

The Hardware in the Trains Lab

32-bit Timer

Base address: 0x80810080

Three registers:

Offset Function R/W Bits
0x0 Timer3Load R/W 32:
0x4 Timer3Value R 32:
0x8 Timer3Control R/W 3:xxx<CLKSEL>xx<MODE><ENABLE>
0xc Timer3Clear W 0: Writing anything clears the interrupt

Interrupt Control Unit (ICU)

All input signals are

Base addresses

Basic Operation

VIC powers up with

Procedure

Initialization

  1. leave protection off
  2. enable in VICxIntEnable when you are ready to handle the interrupt

On an interrupt

  1. Read VICxIRQStatus
  2. Choose which interrupt you wish to handle
  3. Clear the interrupt source in the device

For debugging

  1. Use VICxSoftInt and VICxSoftIntClear to turn interrupt sources off and on in software

Hardware Definitions

Registers for Basic Operation
Register Name Offset R/W Description
VICxIRQStatus 0x00 R One bit for each interrupt source

1 if interrupt is asserted and not masked
VICxFIQStatus 0x04 R As above, for FIQ
VICxRawIntr 0x08 R As above, not masked
VICxIntSelect 0x0c R/W 0: IRQ, 1: FIQ
VICxIntEnable 0x10 R/W 0: Masked, 1: Enabled
VICxIntEnClear 0x14 W Clears bits in VICxIntEnable
VICxSoftInt 0x18 R/W Asserts interrupt from software
VICxSoftIntClear 0x1c W Clears interrupt from software
VICxProtection 0x20 R/W Bit 0 enables protection from user mode access
VICxVectAddr 0x30 R/W Enables priority hardware

See documentation.

Vectored Operation

Procedure

Initialization

  1. Write kernel entry point into VICxDefVectAddr
  2. If desired write special entry point into VICxVectAddry
  3. When ready to accept interrupts write source and enable into VICxVectCntly

When an interrupt occurs

  1. Read VICxVectAddr to find address
  2. Move result to PC
  3. When service is complete write VICxVectAddr to start priority hardware

Look carefully at what's in 0x18

Register Name Offset R/W Description
VICxVectAddr 0x030 R/W Read: address of vector for highest priority interrupt

Write: service complete, enable priority hardware
VICxDefVectAddr 0x034 R/W Default vector address
VICxVectAddry 0x100+4y R/W Vector address for interrupt y
VICxVectCntly 0x200+4y R/W Control register for interrupt y

Bit[0-4]: interrupt source for interrupt y

Bit[5]: enable vectored interrupt y

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