CS452 - Real-Time Programming - Fall 2010

Lecture 16 - UART Interrupts

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The Little Blunder

You may have already read the following.

`It is assumed that various configuration registers for the UART are not written more than once in quick succession, in order to insure proper synchronization of configuration information across the implementation. Such registers include UART1Ctrl and UART1LinCtrlHigh. ... In between the two writes, at least two UARTCLK periods must occur. Under worst case conditions, at least 55 HCLK periods must separate the two writes. The simplest way to due [sic] this is separate the two writes by 55 NOPs.'

Why does this occur?

• CPU clocked by CPU clock
• System buses clocked by several different clocks
• UART clocked by its own clock
• The clocks were not suitably synchronized

Why doesn't anybody care about blunders?

• UARTs are used at the beginning of the development process
• Once other I/O (ethernet, USB, etc.) is working, UARTs are no longer used, except by the boot loader

Interrupts

Five interrupts in the device

1. Transmit
   • FIFO enabled
     • Asserted when transmit FIFO is less than half full.
     • Cleared when transmit FIFO is more than half full.
   • FIFO disabled
     • Asserted when holding register is empty
     • Cleared on write to the holding register
   • Not conditioned by enable.
   • At
     • COM1: Bit 24 of VIC1
     • COM2: Bit 26 of VIC1
2. Receive
   • FIFO enabled
     • Asserted when receive FIFO is half full
     • Cleared when receive FIFO is read to less than half full.
   • FIFO disabled
     • Asserted when receive buffer is full
     • Cleared when receive buffer is read
   • At
     • COM1: Bit 23 of VIC1
     • COM2: Bit 25 of VIC1
3. Modem status
   • Asserted when hardware flow control bits change
   • Cleared when the modem status register is written
4. Receive timeout
   • Asserted when receive FIFO is not empty and 32 bit periods pass with no new data
   • Cleared when all data has been read from FIFO
5. Combined
   • wired OR of the four above interrupts
   • Asserted when at least one of the above interrupts is asserted
   • Cleared when all the above interrupts are not asserted.
   • At
     • COM1: Bit 20 of VIC2
     • COM2: Bit 22 of VIC2

Three inputs to the PIC

1. Transmit
2. Receive
3. Combined

Easy way to use interrupts

Enable only combined; read UART registers to decide what to do.

Think of the receive and transmit parts of the UART as separate state machines

Handy Features

• Loopback state
• Loopback connector
• Terminal as line analyser

Implementation

The simplest way to handle the interrupts is to turn on only the combined interrupt and then look at the registers of the device.

To identify the current interrupt

Read UARTxIntIDIntClr at 0x800[bc]001c

• Four bits, one for each interrupt
• (Write anything to this register to clear the modem status interrupt)

When service is required, without FIFO.

Transmitting

1. Initialization
   • Set up the line control registers: high byte must be written last
     • low: 0x808[cd]0010:[0-7] LSbyte of baud rate divisor
     • middle: 0x808[cd]000c:[0-7] MSbyte of baud rate divisor
     • high: 0x808[cd]0008:[0,1,2,3,4,56]
       • 0: send a break
       • 1: enable/disable parity
       • 2: even/odd parity
       • 3: one/two stop bits
       • 4: enable/disable FIFO
       • 56: number of bits per frame
   • Set up the control register: 0x808[cd]0014:[0, 7]
     • 0: enable/disable UART
     • 7: loopback
   • Read data and discard
   • Enable receive interrupt
   • Enable modem status interrupt: 0x808c0014:[3].
2. When bytes arrive to transmit
   • Add bytes to end of buffer
   • Test CTS: 0x808c0018:[0]
   • If asserted
     • Test transmitter busy: (UARTxFlag at 0x808[cd]0018:[3])
     • If busy
       • enable transmit interrupt (UARTxCtrl at 0x808[cd]0014:[5])
     • else
       • write first byte to hold register (clears interrupt)
       • If more bytes to transmit
         • enable transmit interrupt (UARTxCtrl at 0x800[bc]0014)
3. On transmit interrupt
   • Test CTS
   • If asserted
     • write first byte to hold register (clears interrupt)
     • if no more bytes to transmit
       • disable transmit interrupt
4. On modem status interrupt
   • If OK to send
     • Test transmitter busy
     • If busy
       • Enable transmit interrupt
     • else
       • if bytes to transmit (clears interrupt)
         • write first byte to hold register
         • if more bytes to transmit
           • enable transmit interrupt.

Receiving

1. Receive interrupt
   • Read data (clears interrupt)

Using the FIFO

Left as an exercise.

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