CS452 - Real-Time Programming - Fall 2011

Lecture 31 - Power On II

Public Service Annoucements

1. Acceleration/Deceleration: pdf
2. Second train control demo: 24 November, 2011.
3. Final demo: Tuesday, 6 December, 2011; Wednesday, 7 December, 2011
4. Final exam: 10.30, Friday, 9 December, 2011 to 13.30, Saturday, 10 December, 2011.

Power On

When you turn on the power or press the reset button, what happens before you see the RedBoot> prompt?

• Power on asserts the reset input to the CPU

This is not determined by the instruction set architecture (ISA).

• The ISA guarantees only that the CPU will (at some future time) set the pc to 0x00000000 and start executing instructions.

What happens before that, and what appears at 0x00000000 is determined by the design of the system surrounding the CPU on the chip.

• Cirrus provides this, not ARM.
• What Cirrus provides is pretty generic: the steps are the same on others SoCs, but the details differ.

There are two pretty hard resets that can occur.

1. Turning on the power
2. Pressing the reset button
   • Power-on, but with memory refresh running continuously.

(Jumping to 0x00000000 is a much softer reset.)

Asserting the reset input of the SoC, asserts the reset output of the SoC.

• The output reset goes everywhere and resets everything with a power on reset.

Negating the reset input starts the boot sequence, with the SoC in its reset state. Ten hardware inputs determine how the SoC boots

• internal/external
• pre-boot source
• watchdog state
• bus width of pre-boot and pre-pre-boot

These inputs allow the designer of the board hosting the SoC to determine enough characteristics of the boot state that it can be used for many applications

TS-7200 is set up for internal pre-boot with source from the flash on the 32-bit AHB

The AHB bus has all the important high-speed components

• memory (program and graphics)
• ethernet controller
• USB controller, and
• 16Kbytes of mask-programmed ROM at 0x80090000

Initial state

1. DRAM controller(s) not initialized
2. Flash controller(s) not initialized
3. MMU flat on power up, but might be screwed up on reset
   • SDRAM in 4M blocks at even addresses: not available
     • How many such 4M blocks are there? 1024 = 1K
     • Addresses are
       • 0x00000000 to 0x003fffff
       • 0x00400000 to 0x007fffff
       • 0x00800000 to 0x00bfffff
       • 0x00c00000 to 0x00ffffff
       • 0x01000000 to 0x013fffff
       • etc
     • What is where?
       • 0x00000000 to 0x0fffffff (first 256M) SDRAM
       • 0x10000000 to 0x1fffffff: CS1, 8 bit bus cycles
       • 0x20000000 to 0x2fffffff: CS2, 16 bit bus cycles.
       • 0x60000000 to 0x7fffffff: CS6/7, Flash
       • 0x80000000 to 0x800fffff: AHB mapped registers, including
         • DMA
         • Ethernet
         • USB
         • Memory controllers
         • Pre-pre-boot ROM
         • ICU registers
       • 0x80800000 to 0x8fffffff: I/O registers

     What does this mean? Physical addresses of memory are

     1. 0x00000000 to 0x003fffff
     2. 0x00800000 to 0x00bfffff
     3. 0x01000000 to 0x013fffff
   • flash RAM in one block at 0x60000000: not available
   • AHB registers in 0x80000000 to 0x800fffff

In the AHB registers is a 16K block of ROM from 0x80090000 to 0x80093fff

• Initially, it is mapped to the entire memory space at 16K intervals.
• Chip select, and how addressing occurs.
  • Chip select of this block is 0x8009[00XXb]XXX
  • Chip select has two parts
    1. AHB chip select: 0x800XXXXX
• The first instruction executed is the one that you find at 0x80090000
• How much code is there
  • 4K words, but code repeated 4 times
  • 1K words of unique code, but only half is unique executable code

There is almost no context

Pre-pre-boot Sequence

1. Jump to 0x80090018.
2. Turn on LEDs
3. Disable watchdog timer
4. Make the CPU completely vanilla. E.g.,
   • caches, MMU, branch prediction, alignment checking, all disabled
   • write buffer enabled
   • 32-bit addressing
   • little-endian
   • normal exception vectors
   • predictable cache replacement
5. Acquire boot state (for bus width) to set up 6 static memory controllers
6. Acquire boot state (for bus width) to set up 4 dynamic memory controllers
7. Clear boot mode `memory map'
8. Acquire configuration inputs
   • These are input pins on the EP9302, the state of which is determined by the TS7200.
   • A couple are user-controllable via jumpers
   • They are the only thing the EP9302 knows about the outside world
9. Switch
   • Serial boot on UART1
     1. Output ">"
     2. Read 2048 bytes starting with CRUS to the ethernet buffer
     3. Jump to the start of the ethernet buffer
   • Boot from ROM outside SoC
     1. Assert ROM chip selects looking for CRUS
     2. When found read 2048 bytes from the ROM to ethernet buffer
     3. Jump to the start of the ethernet buffer
   • Boot from flash
     1. Look for CRUS at possible flash start locations
     2. When found jump to start location plus 0x4
10. In the first two cases the 2048 bytes contains a memory test followed by a loader.

Pre-boot Sequence

This code knows all about the EP9302, and all about the TS7200.

1. Sets up a stack in the ethernet buffer
2. Sets the CPSR to a vanilla state: no interrupts, svc mode
3. Set up stack pointer in Mac FIFO
4. Copies 260 words of code from flash to Mac FIFO
5. Initializes memory controllers for the memory it has
6. Configures GPIO.
7. Turns off the watchdog timer
8. Sets up the appropriate serial port for a monitor

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