CS452 - Real-Time Programming - Spring 2009

Lecture 16 - Serial Hardware

Practical Details

Interrupt Handling

1. How are you handling hardware interrupts?
   • One entry for hardware and software
   • One entry for software, a different one for hardware
   • One entry for software, several entries for hardware

Serial Hardware

See pdf.

FIFO

Why do FIFOs exist in UARTS?

Interrupts

Five interrupts in the device

1. Transmit
   • Asserted when transmit FIFO is less than half full.
   • Cleared when transmit FIFO is more than half full.
   • Not conditioned by enable.
2. Receive
   • Asserted when receive FIFO is half full
   • Cleared when receive FIFO is read to less than half full.
3. Modem status
   • Asserted when hardware flow control bits change
   • Cleared when the modem status register is written
4. Receive timeout
   • Asserted when receive FIFO is not empty and 32 bit periods pass with no new data
   • Cleared when all data has been read from FIFO
5. Combined
   • OR of the four above interrupts
   • Asserted when at least one of the above interrupts is asserted
   • Cleared when all the above interrupts are not asserted.

Three inputs to the PIC

1. Transmit
2. Receive
3. Combined

Easy way to use interrupts

Enable only combined; read UART registers to decide what to do.

Think of the receive and transmit parts of the UART as separate state machines

Handy Features

Loopback

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