CS452 - Real-Time Programming - Spring 2010

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Lecture 13 - ARM Interrupts

General Hardware Interrupts

Kernel Provision for Interrupts

  1. Initialize the kernel with interrupts disabled
  2. Turn on interrupts by having user PSW with interrupts enabled
  3. Find source of interrupt
  4. Turn off source of interrupt
  5. Handle interrupt
  6. Reschedule and activate

Three Free Choices

  1. Rescheduling
  2. Volatile Data
  3. Re-enabling interrupts

The Primitive for Hardware Interrupts: AwaitEvent

int AwaitEvent( int evtType )

Blocking

  1. Calling task is made EVENT_BLOCKED
  2. Calling task is made READY when the evemt occurs

Interjection

How is AwaitEvent Used?

  1. There should (almost) always be a task blocked on AwaitEvent for every interrupt type. Why?
  2. A server cannot call AwaitEvent. Why?
  3. We call the task that calls AwaitEvent a Notifier. Why?
  4. Code for a typical Notifier 
    main( ) {
    Tid server;
    int evtType, data;
    Receive( &server, &evtType, ... );
    // Other initialization
    Reply( server, ... );
    FOREVER {
        data = AwaitEvent( evtType );
        Send( server, &data, ... );
    }
}
  5. Code for a typical server 
    main( ) {
    notifier = Create( HIGHEST, ... );
    // other initialization
    Send( notifier, &evtType, ... );
    FOREVER {
        Receive( &requester, &request, ... );
        switch ( request.type ) {
        case NOTIFIER:
            data = request.data;
            Reply( notifier );
            break;
        case CLIENT:
            ...
        }
    }
}

End of Interjection

Argument

  1. Somewhere there is a list of event types
  2. This is not very portable

Return value

Related to three free choices above.

Strategy 1: Kernel does it all

Strategy 2: Notifier does most of it

HALT versus an Idle Task

What do you do when there are no tasks to run?

HALT

The Hardware in the Trains Lab

Timer

Interrupt Control Unit (ICU)

All input signals are

Base addresses

Basic Operation

VIC powers up with

Procedure

Initialization

  1. leave protection off
  2. enable in VICxIntEnable when you are ready to handle the interrupt

On an interrupt

  1. Read VICxIRQStatus
  2. Choose which interrupt you wish to handle
  3. Clear the interrupt source in the device

For debugging

  1. Use VICxSoftInt and VICxSoftIntClear to turn interrupt sources off and on in software

Hardware Definitions

Registers for Basic Operation
Register Name Offset R/W Description
VICxIRQStatus 0x00 RO One bit for each interrupt source

1 if interrupt is asserted and not masked
VICxFIQStatus 0x04 RO As above for FIQ
VICxRawIntr 0x08 RO As above but not masked
VICxIntSelect 0x0c R/W 0: IRQ, 1: FIQ
VICxIntEnable 0x10 R/W 0: Masked, 1: Enabled
VICxIntEnClear 0x14 WO Clears bits in VICxIntEnable
VICxSoftInt 0x18 R/W Asserts interrupt from software
VICxSoftIntClear 0x1c WO Clears interrupt from software
VICxProtection 0x20 R/W Bit 0 enables protection from user mode access
VICxVectAddr 0x30 R/W Enables priority hardware

See documentation.

Vectored Operation

Procedure

Initialization

  1. Write kernel entry point into VICxDefVectAddr
  2. If desired write special entry point into VICxVectAddry
  3. When ready to accept interrupts write source and enable into VICxVectCntly

When an interrupt occurs

  1. Read VICxVectAddr to find address
  2. Move result to PC
  3. When service is complete write VICxVectAddr to start priority hardware
Register Name Offset R/W Description
VICxVectAddr 0x030 R/W Read: address of vector for highest priority interrupt

Write: service complete, enable priority hardware
VICxDefVectAddr 0x034 R/W Default vector address
VICxVectAddry 0x100+4y R/W Vector address for interrupt y
VICxVectCntly 0x200+4y R/W Control register for interrupt y

Bit[0-4]: interrupt source for interrupt y

Bit[5]: enable vectored interrupt y

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