CS452 - Real-Time Programming - Spring 2010

Public Interest Announcements

Lecture 15 - Serial I/O

See pdf.

FIFO

Why do FIFOs exist in UARTS?

The Big Blunder

To use the FIFO effectively you must be able to turn off the transmitter & receiver independently.

But look at UARTE in UARTxCtrl

• UART Enable.
• If this bit is set to 1, the UART is enabled.
• Data transmission and reception occurs for UART signals.

The Little Blunder

`It is assumed that various configuration registers for the UART are not written more than once in quick succession, in order to insure proper synchronization of configuration information across the implementation. Such registers include UART1Ctrl and UART1LinCtrlHigh. ... In between the two writes, at least two UARTCLK periods must occur. Under worst case conditions, at least 55 HCLK periods must separate the two writes. The simplest way to due [sic] this is separate the two writes by 55 NOPs.'

Why does this occur?

• CPU clocked by CPU clock
• System buses clocked by several different clocks
• UART clocked by its own clock
• The clocks were not suitably synchronized

Why doesn't anybody care?

• UARTs are used at the beginning of the development process
• Once other I/O (ethernet, USB, etc.) is working, UARTs are no longer used, except by the boot loader

Interrupts

Five interrupts in the device

1. Transmit
   • FIFO enabled
     • Asserted when transmit FIFO is less than half full.
     • Cleared when transmit FIFO is more than half full.
   • FIFO disabled
     • Asserted when holding register is empty
     • Cleared on write to the holding register
   • Not conditioned by enable.
2. Receive
   • FIFO enabled
     • Asserted when receive FIFO is half full
     • Cleared when receive FIFO is read to less than half full.
   • FIFO disabled
     • Asserted when receive buffer is full
     • Cleared when receive buffer is read
3. Modem status
   • Asserted when hardware flow control bits change
   • Cleared when the modem status register is written
4. Receive timeout
   • Asserted when receive FIFO is not empty and 32 bit periods pass with no new data
   • Cleared when all data has been read from FIFO
5. Combined
   • OR of the four above interrupts
   • Asserted when at least one of the above interrupts is asserted
   • Cleared when all the above interrupts are not asserted.

Three inputs to the PIC

1. Transmit
2. Receive
3. Combined

Easy way to use interrupts

Enable only combined; read UART registers to decide what to do.

Think of the receive and transmit parts of the UART as separate state machines

Handy Features

Loopback

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• Bill Cowan's Spring 2010 CS452 page
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