CS452 - Real-Time Programming - Spring 2011

Lecture 10 - Hardware Interrupts

Pubilic Service Announcement

1. Kernel 1 marks

Servers

What is a server?

• a task that provides service to a client task
  • tasks requesting service, clients, must know the Tid of the server
• a task that owns a resource and provides synchronized access to it.
• above,
  • `a task' owns the interface
  • other tasks may do the work

How are servers implemented?

• Receive is the key
  • Receive a request
  • Reply the response
• Sender (client, task that is making the request) blocks until the response is available. That is, sender, in effect, is running at the priority of the server between the request and its reponse
  • Server priority should be set according to the importance of the service it supplies.
  • But client priority should be considered by the server. For example,
    • One set of instructions for higher priority client
    • One set of instructions for lower priority client

Name Server

What is a name server?

• There is a set of global execution-independent names
• There is a set of execution-dependent tasks that provide services associated with the names
• Name server maintains an up-to-date table mapping names to resources
  • Accepts requests to update the table
  • Accepts queries concerning the table

Why Do We Need a Name Server

How do You Get the Task Id of the Name Server?

1. Make it a constant across executions

Name Server API

int RegisterAs( char *name );

• One task can be registered under two names.
• Each name is associated with a single task.
• Name is \000 terminated.

int WhoIs( char *name );

• Name is \000 terminated.

Name Server Semantics

RegisterAs

• Errors
  1. Not a legal name.
     • It's up to you to decide what you will accept as legal names
  2. tid is not a task
  3. tid is not the Name Server
  4. Already somebody registered with that name
     • What does the caller do?

WhoIs

• Errors
  1. Not a legal name.
  2. tid is not a task
  3. tid is not the Name Server
  4. No task registered under that name
     • What does the caller do?

Comments

• RegisterAs overwrites.
• Why? The rule is that the name -> task map is many to one.
  • A task may have many names
  • A name may have only one task

Name Server Implementation

User Code

E.g., RegisterAs

typedef struct {
    int type;
    char *name;
} NSstruct;
int RegisterAs( char *name ) {
    int result;
    NSstruct req;
    req.type = REGISTERAS;
    req.name = name;
    bytes = Send( NSTid, &req, sizeof(NSstruct), (char *) result, sizeof(int) );
    if ( bytes != sizeof(int) ) {
        // Do something error-like
    } else return result;
}

There are lots of possible variations, and this one is by no means the best.

Server Code

typedef struct {
    int type;
    char name[MaxNameSize];
} NSstruct;
int bytes, tid, result;
NSstruct req;
// initialize tables
FOREVER {
    bytes = Receive( &tid, &req, sizeof(NSstruct) );
    if ( detectError( ... ) ) {
        // Reply with error
    } else {
        switch( req.type ) {
        case REGISTERAS:
            insert( req.name, tid );
            Reply( tid, SUCCESS, sizeof(int) );
            break;
        case WHOIS:
            result = lookup( name );
            Reply( tid, result, sizeof(int) );
            break;
        default:  // This should never happen
            Reply( tid, ERROR, sizeof(int) );
            break;
        }
    }
}

Comments

1. How much will this code run?
   • When will it run?
2. How would you implement insert & lookup?
   • Figure out
     1. What deadlines does Nameserver have?
     2. How many names will be in NameServer?
     3. How many ReisterAs? and when?
     4. How many WhoIs? and when?

What should be allowable as a name?

Hardware Interrupts

What is a Hardware Interrupt?

In the CPU

1. Test interrupt signal before fetching the next instruction
   • actually AND of INT and CPSR bit
2. If asserted, change mode to IRQ
3. Disable interrupt in CPSR
4. Execute instruction at 0x18

In the Interrupt Control Unit (ICU)

• Several interrupts may be present when an interrupt occurs
  • One is chosen, by a priority mechanism
  • Put in a special place
  • Software can choose to ignore priority mechanism in ICU
• Clearing one interrupt may just expose another one

In the Peripheral Hardware

• Several interrupts may be present
  • ORed in peripheral hardware
  • ORed in glue hardware
  • Rare that there is a priority mechanism
• Clearing one interrupt can expose another one

When two interrupts are present

May have been two present when interrupt processing started

• in which case interrupt occurring now is known to be of lower priority

May have occurred since interrupt processing started

• in which case interrupt occurring now may be of higher priority

What happens next?

1. Kernel executes with interrupts disabled
2. Context switch into user task turns on interrupts
3. Before fetching the first user task instruction test interrupt signal
4. If asserted, re-initiate interrupt processing

Context Switches for Interrupts

Difference from Software Interrupts

It is impossible to predict where they occur

• You may have made some assumptions about when they occur

Assymmetry between User Task and Kernel

Scratch Registers must be saved

• including the IP

Two Link Registers

1. One to return from interrupt
   • In the registers of the interrupt handling code
   • To return to the interrupted task in the right place
2. One to move to the caller's stack frame
   • In the registers of the interrupted task
   • To return to whatever started in interrupted task

Helpful Features of the ICU

1. Several places where you can read state
2. Several places where you can block interrupt flow
3. Trigger hardware interrupt from software
   • What makes interrupts hard is that you are doing two semi-hard things at once
     1. Making the hardware produce the interrupt
     2. Responding to the interrupt
   • This allows you to separate them in developing/debugging

Kernel Provision for Interrupts

1. Initialize the kernel with interrupts disabled
2. Turn on interrupts by having user PSW with interrupts enabled
   • First instruction of user task might not execute immediately
3. Find source of interrupt
   • Query ICU
   • Query device
4. Turn off source of interrupt
   • In device
   • In ICU
   • PSR remains with IRQ disabled
5. Handle interrupt
   • Find waiting task
   • Make waiting task READY
6. Reschedule and activate

Three Free Choices

1. Rescheduling
2. Volatile Data
3. Re-enabling interrupts

The Hardware in the Trains Lab

Timer

Interrupt Control Unit (ICU)

All input signals are

• active high
• level sensitive

Base addresses

• VIC1: 0x800B0000
• VIC2: 0x800C0000

Basic Operation

VIC powers up with

• all vectored interrupts disabled.
• all interrupts masked
• all interrupts giving IRQ

Procedure

Initialization

1. leave protection off
2. enable in VICxIntEnable when you are ready to handle the interrupt

On an interrupt

1. Read VICxIRQStatus
2. Choose which interrupt you wish to handle
3. Clear the interrupt source in the device

For debugging

1. Use VICxSoftInt and VICxSoftIntClear to turn interrupt sources off and on in software

Hardware Definitions

Vectored Operation

Procedure

Initialization

1. Write kernel entry point into VICxDefVectAddr
2. If desired write special entry point into VICxVectAddry
3. When ready to accept interrupts write source and enable into VICxVectCntly

When an interrupt occurs

1. Read VICxVectAddr to find address
2. Move result to PC
3. When service is complete write VICxVectAddr to start priority hardware

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