CS452 - Real-Time Programming - Spring 2011

Lecture 11 - ARM Interrupts

Pubilic Service Announcement

1. Kernel 1 comments

Hardware Interrupts

What is a Hardware Interrupt?

What the CPU does for you

1. Test interrupt signal before fetching the next instruction
   • actually AND of INT and CPSR bit
2. If asserted, change mode to IRQ
3. Disable interrupt in CPSR
4. Execute instruction at 0x18

In the Interrupt Control Unit (ICU)

• Vectored operation is possible: several interrupts may be present when an interrupt occurs
  • One is chosen, by a priority mechanism
  • Put in a special place
  • Software can choose to ignore priority mechanism in ICU
• Clearing one interrupt may just expose another one

In the Peripheral Hardware

• Several interrupts may be present
  • ORed in peripheral hardware
  • ORed in glue hardware
  • Rare that there is a priority mechanism
• Clearing one interrupt can expose another one

When two interrupts are present

May have been two present when interrupt processing started

• in which case interrupt occurring now is known to be of lower priority

May have occurred since interrupt processing started

• in which case interrupt occurring now may be of higher priority

What happens next?

1. Kernel executes with interrupts disabled
2. Context switch into user task turns on interrupts
3. Before fetching the first user task instruction test interrupt signal
4. If asserted, re-initiate interrupt processing

Kernel Provision for Interrupts

1. Initialize the kernel with interrupts disabled
2. Turn on interrupts by having user PSW with interrupts enabled
   • First instruction of user task might not execute immediately
3. Find source of interrupt
   • Query ICU
   • Query device
4. Turn off source of interrupt
   • In device
   • In ICU
   • PSR remains with IRQ disabled
5. Handle interrupt
   • Find waiting task
   • Make waiting task READY
6. Reschedule and activate

Three Free Choices

1. Rescheduling
2. Volatile Data
3. Re-enabling interrupts

The Hardware in the Trains Lab

32-bit Timer

Base address: 0x80810080

Three registers:

Interrupt Control Unit (ICU)

ARM PL190.

The logic in this design is completely asynchronous, so it functions when the CPU clock is turned off.

• Important (= essential) for low power operation.

All input signals from device are

• active high
• level sensitive

Base addresses

• VIC1: 0x800B0000
• VIC2: 0x800C0000

Basic Operation

VIC powers up with

• all vectored interrupts disabled.
• all interrupts masked
• all interrupts giving IRQ (not FIQ)
• protection off

Procedure

Initialization

1. leave protection off
2. enable in VICxIntEnable when you are ready to handle the interrupt

On an interrupt

1. Read VICxIRQStatus
2. Choose which interrupt you wish to handle
3. Clear the interrupt source in the device

For debugging

1. Use VICxSoftInt and VICxSoftIntClear to turn interrupt sources off and on in software

Hardware Definitions

Helpful Features of the ICU

1. Several places where you can read state
2. Several places where you can block interrupt flow
3. Trigger hardware interrupt from software
4. What makes interrupts hard is that you are doing two semi-hard things at once
   1. Making the hardware produce the interrupt
   2. Responding to the interrupt
   3. This allows you to separate them in developing/debugging

Non-vectored Operation

Initialization

1. Enable interrupt in device
2. Enable interrupt in ICU
3. Enable interrupt in CPU, usually by MOVS

Interrupt occurs

1. AND of IRQ and NOT( IRQ disabled ) is checked before each instruction fetch.
2. If set IRQ exception is taken in place of next instruction fetch.
   • Possibly zero instructions of active task are executed.
   • Make sure that this case works
3. Context switch into kernel

   ---

   Context switch novelties

   Difference from Software Interrupts

   • It is impossible to predict where they occur
   • You probably made some assumptions about when they occur
   • Scratch Registers must be saved
     • r0-3
     • IP
   • Two Link Registers
     • One to return from interrupt
     • One to return from the interrupted task to whatever called it

   ---

4. Turn off interrupt in device
   • Should turn off interrupt in ICU
   • What about IRQ?

You are now ready to process the interrupt in the kernel

Vectored Operation

Procedure

Initialization

1. Write kernel entry point into VICxDefVectAddr
2. If desired write special entry point into VICxVectAddry
3. When ready to accept interrupts write source and enable into VICxVectCntly

When an interrupt occurs

1. Read VICxVectAddr to find address
2. Move result to PC
3. When service is complete write VICxVectAddr to start priority hardware

Look carefully at what's in 0x18

• Usually, ldr pc, [pc, #offset]
• <IRQ> is the offset from the pc to the kernel entry
• How is the instruction encoded
  • 31:28 - condition codes
  • 27:20 - op code and flags, 0101<offset sign>001
  • 19:16 - base register
  • 15:12 - destination register
  • 11:00 - 12-bit offset
• With a 12 bit offset and pc=0x18 you can address
  • from 0x18 + 0x8 - 0xffc = -0xfdc =0xfffff020
  • to 0x18 + 0x8 + 0xffc = 0x1020
• You could have the kernel entry point in
  • either 0x800b0030
  • or 0x800c0030
• Both are out of range. What could you do?

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