CS452 - Real-Time Programming - Spring 2011

Lecture 29 - Power On

Pubilic Service Announcement

1. UI is hard
2. Build in increments. Save last^H^H^H^Hevery working version!!
3. Reservation system needs to be tunable. Making this work robustly will be time consuming.
4. Modularity is good; distributed control is good; many tasks, but not too many, is good;

Power On

When you turn on the power or press the reset button, what happens before you see the RedBoot> prompt?

This is not determined by the instruction set architecture (ISA).

• The ISA guarantees only that the CPU will (at some future time) set the pc to 0x00000000 and start executing instructions.

What happens before that, and what appears at 0x00000000 is determined by the design of the system surrounding the CPU on the chip.

• Cirrus provides this, not ARM.
• What Cirrus provides is pretty generic: the steps are the same on others SoCs, but the details differ.

There are two pretty hard resets that can occur.

1. Turning on the power
2. Pressing the reset button
   • Power-on, but with memory refresh running continuously.

(Jumping to 0x00000000 is a much softer reset.)

Asserting either of the input reset pin on the SoC, asserts the output reset pin on the SoC.

• The output reset goes everywhere and resets everything with a power on reset.

Negating the reset input starts the boot sequence, with the SoC in its reset state. Ten hardware inputs determine how the SoC boots

• internal/external
• pre-boot source
• watchdog state
• bus width of pre-boot and pre-pre-boot

TS-7200 is set up for internal pre-boot with source from the flash on the 32-bit AHB

The AHB bus has all the important high-speed components

• memory (program and graphics)
• ethernet controller
• USB controller, and
• 16Kbytes of mask-programmed ROM at 0x80090000

Initial state

1. DRAM controller not initialized
2. Flash controller not initialized
3. MMU flat on power up, but might be screwed up on reset
   • SDRAM in 4M blocks at even addresses: not available
   • flash RAM in one block at 0x60000000: not available
   • AHB registers in 0x80000000 to 0x800fffff

In the AHB registers is a 16K block of ROM from 0x80090000 to 0x80093fff

• Initially, it is mapped to the entire memory space at 16K intervals.
• Chip select, and how addressing occurs.
• The first instruction executed is the one that you find at 0x80090000

There is almost no context

Pre-pre-boot Sequence

1. Jump to 0x80090018.
2. Turn on LEDs
3. Make the CPU completely vanilla. E.g.,
   • no caches, physical memory map,
4. Turn off watchdog timer
5. Acquire boot state
6. Configure external clocks (needed for serial boot)
7. Using boot state configure
   • flash memory controller
   • SDRAM memory controller

   These are configured with very conservative parameters

8. Clear boot mode `memory map'
9. Acquire configuration inputs
   • These are input pins on the EP9302, the state of which is determined by the TS7200.
   • A couple are user-controllable via jumpers
   • They are the only thing the EP9302 knows about the outside world
10. Switch
    • Serial boot on UART1
      1. Output ">"
      2. Read 2048 bytes starting with CRUS to the ethernet buffer
      3. Jump to the start of the ethernet buffer
    • Boot from ROM outside SoC
      1. Assert ROM chip selects looking for CRUS
      2. When found read 2048 bytes from the ROM to ethernet buffer
      3. Jump to the start of the ethernet buffer
    • Boot from flash
      1. Look for CRUS at possible flash start locations
      2. When found jump to start location plus 0x4
11. In the first two cases the 2048 bytes contains a memory test followed by a loader.

Pre-boot Sequence

This code knows all about the EP9302, and all about the TS7200.

1. Sets up a stack in the ethernet buffer
2. Sets the CPSR to a vanilla state: no interrupts, svc mode
3. Copies 260 words of code from flash to the ethernet buffer
4. Initializes memory controllers for the memory it has
5. Configures GPIO.
6. Turns off the watchdog timer
7. Sets up the appropriate serial port for a monitor

Return to:

• Bill Cowan's lecture notes for CS452 in s11
• Bill Cowan's Spring 2011 CS452 page
• Bill Cowan's CS452 page
• Bill Cowan's teaching pagelu