CS452 - Real-Time Programming - Spring 2012

Lecture 30 - Power On

Public Service Annoucements

1. Final exam date: 9.00 August 7 to 11.30 August 9

Power On

When you turn on the power or press the reset button, what happens before you see the RedBoot> prompt?

• Power on asserts the reset input to the CPU

This is not determined by the instruction set architecture (ISA).

• The ISA guarantees only that the CPU will (at some future time) set the pc to 0x00000000 and start executing instructions.

What happens before that, and what appears at 0x00000000 is determined by the design of the system surrounding the CPU on the chip.

• Cirrus provides this, not ARM.
• What Cirrus provides is pretty generic: the steps are the same on others SoCs, but the details differ.

There are two pretty hard resets that can occur.

1. Turning on the power
2. Pressing the reset button
   • Power-on, but with memory refresh running continuously.

(Jumping to 0x00000000 is a much softer reset.)

Asserting the reset input of the SoC, asserts the reset output of the SoC.

• The output reset goes everywhere and resets everything with a power on reset.

Negating the reset input starts the boot sequence, with the SoC in its reset state. Ten hardware inputs determine how the SoC boots

• internal/external
• pre-boot source
• watchdog state
• bus width of pre-boot and pre-pre-boot

These inputs allow the designer of the board hosting the SoC to determine enough characteristics of the boot state that it can be used for many applications

TS-7200 is set up for internal pre-boot with source from the flash on the 32-bit AHB

The AHB bus has all the important high-speed components

• memory (program and graphics)
• ethernet controller
• USB controller, and
• 16Kbytes of mask-programmed ROM at 0x80090000

Initial state

ARM

The following things, which are contolled through the system control co-processor, are determined by the CPU architecture. They must be independent of the stuff added by Cirrus

1. MMU flat, but might be different on soft reset
2. Caches disabled
3. Slow bus clock
4. Interrupts disabled
5. Little-endian memory system
6. No access to MMU registers
7. Normal exception registers

Cirrus

The following things, which are described in the EP9302 documentation, are properties of hardware Cirrus added. They are independent of how Technologic configured the chip when they designed the TS7200.

1. DRAM controller(s) not initialized
2. Flash controller(s) not initialized
3. All I/O devices in reset state. (They receive hardware reset inputs from the CPU.)
4. Memory map in boot mode

Technologic

The following things, which are described in the Technologic documentation, manual & circuit diagram, are properties of the TS7200

1. Boot control bits, set to normal boot, 32-bit bus width, sychronous boot device, internal, watchdog timer disabled.
2. Physical memory map
   • 0x80000000 to 0x800fffff, used by Cirrus for on-chip components
   • SDRAM chips break memory into 4M blocks. Addresses of 4M blocks are
     • 0x00000000 to 0x003fffff
     • 0x00400000 to 0x007fffff
     • 0x00800000 to 0x00bfffff
     • 0x00c00000 to 0x00ffffff
     • 0x01000000 to 0x013fffff
     • ...
   • TS7200 uses 4-bit chip select to divide the memoery into 256 Mbyte blocks
     • 0x00000000 to 0x0fffffff (first 256M) SDRAM, CS0, 32 bus cycles
     • 0x10000000 to 0x1fffffff: CS1, 8 bit bus cycles
     • 0x20000000 to 0x2fffffff: CS2, 16 bit bus cycles.
     • 0x60000000 to 0x7fffffff: CS6/7, Flash
     • 0x80000000 to 0x8fffffff: I/O registers including
       • 0x80000000 to 0x807fffff: AHB mapped registers, including
         • DMA
         • Ethernet
         • USB
         • Memory controllers
         • Pre-pre-boot ROM
         • ICU registers
       • 0x80800000 to 0x8fffffff: I/O registers

     SDRAM chips break memory into 4M blocks. Addresses of 4M blocks are

   • 0x00000000 to 0x003fffff
   • 0x00400000 to 0x007fffff
   • 0x00800000 to 0x00bfffff
   • 0x00c00000 to 0x00ffffff
   • 0x01000000 to 0x013fffff
   • ...
3. In the AHB registers is a 16K block of ROM from 0x80090000 to 0x80093fff
   • Initially, it is mapped to the entire memory space at 16K intervals.
   • Chip select, and how addressing occurs.
     • Chip select of this block is 0x8009[00XXb]XXX
     • Chip select has two parts
       • I/O chip select: 0x8XXXXXXX
       • AHB chip select: 0xY00XXXXX
       • ROM chip select: 0xYYY9[00XXb]XXX
   • The first instruction executed is the one that you find at 0x80090000

Pre-pre-boot Sequence

1. Jump to 0x80090018.
2. Turn on LEDs
3. Make the CPU completely vanilla. E.g.,
   • no caches, physical memory map,
4. Turn off watchdog timer
5. Acquire boot state
6. Configure external clocks (needed for serial boot)
7. Acquire boot state configuration inputs
   • These are input pins on the EP9302, the state of which is determined by the TS7200.
   • A couple are user-controllable via jumpers
   • They are the only thing the EP9302 knows about the outside world
8. Using boot state configure
   • flash memory controller
   • SDRAM memory controller

   These are configured with very conservative parameters

9. Clear boot mode `memory map'
10. Toggle LEDs
11. Switch
    • Serial boot on UART1
      1. Output ">"
      2. Read 2048 bytes starting with CRUS or SURC to the ethernet buffer
      3. Jump to the start of the ethernet buffer
    • Boot from ROM outside SoC
      1. Assert ROM chip selects looking for CRUS
      2. When found read 2048 bytes from the ROM to ethernet buffer
      3. Jump to the start of the ethernet buffer
    • Boot from flash
      1. Look for CRUS at possible flash start locations
      2. When found jump to start location plus 0x4 (account for CRUS)
      3. If not found
         • load code into ethernet buffer
         • flash LEDs forever
12. In the first two cases the 2048 bytes contains a memory test followed by a loader.

Pre-boot Sequence

This code knows all about the EP9302, and all about the TS7200.

1. Sets up a stack in the ethernet buffer
2. Sets the CPSR to a vanilla state: no interrupts, svc mode
3. Copies 260 words of code from flash to the ethernet buffer
4. Initializes memory controllers for the memory it has
5. Configures GPIO.
6. Turns off the watchdog timer
7. Sets up the appropriate serial port for a monitor

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