CS452 - Real-Time Programming - Spring 2013

Lecture 12 - Context Switch Redux

Pubilc Service Annoucements

  1. Due date for kernel 2: 3 June.

Hardware Interrupts

What is a Hardware Interrupt?

In the CPU

  1. Test interrupt signal before fetching the next instruction
  2. If asserted, change mode to IRQ
  3. Disable interrupt in CPSR
  4. Put CPSR into SPSR_irq
  5. Execute instruction at 0x18

In the Interrupt Control Unit (ICU)

In the Peripheral Hardware

When two interrupts are present

What should happen?

  1. Kernel executes with interrupts disabled.
  2. Context switch into user task turns on interrupts.
  3. Before fetching the first user task instruction test IRQ input.
  4. If asserted, re-initiate interrupt processing.

Context Switches for Interrupts

Difference from Software Interrupts

It is impossible to predict when hardware interrupts occur ( = where the PC is)

Assymmetry between User Task and Kernel

For the interrupted task,

  1. scratch registers must be saved and restored, including IP
  2. stack pointer must be stored
  3. two link registers must be kept separate

For the kernel,

  1. no need to save scratch registers
  2. stack pointer preserved in S13_svc
  3. link register preserved in R14_svc

Two Link Registers

  1. One to return from interrupt
  2. One to move to the caller's stack frame

Helpful Features of the ICU

  1. Several places where you can read state
  2. Several places where you can block interrupt flow
  3. Trigger hardware interrupt from software

The Hardware in the Trains Lab

32-bit Timer

Base address: 0x80810080

Three registers:

Offset Function R/W Bits Comments
0x0 Timer3Load R/W 32: <Load/Reload Value>
0x4 Timer3Value R 32:<Current value> Set when Load is written,
even when counting
0x8 Timer3Control R/W 3:xxx<CLKSEL>xx<MODE><ENABLE> <CLKSEL>: 0, 2KHz clock; 1, 508KHz
<MODE>: 1, count continuously; 0, count once
<ENABLE>: Clock turned on
0xc Timer3Clear W 32: Writing anything clears the interrupt

Interrupt Control Unit (ICU)

The actual device is the ARM PL190

The logic in this design is completely asynchronous, so it functions when the CPU clock is turned off.

All input signals are

Base addresses

Basic Operation

VIC powers up with

Procedure

Initialization

  1. leave protection off
  2. enable in VICxIntEnable when you are ready to handle the interrupt

On an interrupt

  1. Read VICxIRQStatus
  2. Choose which interrupt you wish to handle
  3. Clear the interrupt source in the device

For debugging

  1. Use VICxSoftInt and VICxSoftIntClear to turn interrupt sources off and on in software

Hardware Definitions

Registers for Basic Operation
Register Name Offset R/W Description
VICxIRQStatus 0x00 RO One bit for each interrupt source

1 if interrupt is asserted and enabled

VICxFIQStatus 0x04 RO As above for FIQ
VICxRawIntr 0x08 RO As above but not masked
VICxIntSelect 0x0c R/W 0: IRQ, 1: FIQ
VICxIntEnable 0x10 R/W 0: Masked, 1: Enabled
VICxIntEnClear 0x14 WO Clears bits in VICxIntEnable
VICxSoftInt 0x18 R/W Asserts interrupt from software
VICxSoftIntClear 0x1c WO Clears interrupt from software
VICxProtection 0x20 R/W Bit 0 enables protection from user mode access
VICxVectAddr 0x30 R/W Enables priority hardware

See documentation.

Helpful Features of the ICU

  1. Several places where you can read state
  2. Several places where you can block interrupt flow
  3. Trigger hardware interrupt from softwareonce
    1. What makes interrupts hard is that you are doing two semi-hard things at once
      • Making the hardware produce the interrupt
      • Responding to the interrupt
    2. Software interrupt generation allows you to separate them in developing/debugging


Non-vectored Operation

Initialization

  1. Enable interrupts in device
  2. Enable interrupts in ICU
  3. Enable interrupts in CPU, usually by MOVS

Interrupt occurs

  1. AND of IRQ and NOT( IRQ disabled bit in CPSR ) is checked before each instruction fetch.
  2. If set IRQ exception is taken in place of next instruction fetch.
  3. Context switch into kernel

    Context switch novelties

    Difference from Software Interrupts


  4. Turn off interrupt in device

You are now ready to process the interrupt in the kernel


Clock Server, Task Structure

A New Kernel Primitive: int AwaitEvent( int EventType )

How is AwaitEvent Used?

  1. There should (almost) always be a task blocked on AwaitEvent for every interrupt type. Why?
  2. A server cannot call AwaitEvent. Why?
  3. We call the task that calls AwaitEvent a Notifier. Why?
  4. Code for a typical Notifier
    void notifier( ) {
        Receive( &server, &evtType, ... );
        // Initialization, probably including device
        Reply( server, ... );
        FOREVER {
            data = AwaitEvent( evtType );
            Send( server, &data, ... );
        }
    }
  5. Code for a typical server
    void server( ) {
        notifier = Create( HIGHEST, ... );
        // other initialization
        Send( notifier, &evtType, ... );
        FOREVER {
            Receive( &requester, &request, ... );
            switch ( request.type ) {
            case NOTIFIER:
                Reply( notifier );
                data = request.data;
                // use data
            case CLIENT:
                ...
            }
        }
    }

More About AwaitEvent

Argument

  1. Somewhere there is a list of event types
  2. This is not very portable

Processing in the kernel

HALT versus an Idle Task

What do you do when there are no tasks to run?


Clock Server

Primitives

int Time( )
int Delay( int ticks )
int DelayUntil( int ticks )

Pseudo-implementation

void clock( ) {
    // Create Notifier and send  any initialization data
    // Initialize self
    FOREVER {
        Receive( &requester, &request, ... );
        switch ( request.type ) {
        case NOTIFIER:
            Reply( notifier, ... )
            // update time
        case TIME_REQUEST:
            Reply( requester, time,... )
        case DELAY_REQUEST: 
            // Add requester to list of suspended tasks
        }
        // Reply to any timed-out tasks
    }
}

Comments:

  1. You need a common request type, or possibly a union.
  2. You should notice a typical server pattern.

It's normal to sort the list of suspended tasks. Why?


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